logical.v

verilog, TMSC6415 S单元代码

module  logical (DC_B_Src1,DC_B_Src2,DC_AND,DC_OR,DC_XOR,DC_ANDN,logical_out);
   input DC_AND;
   input DC_OR;
   input DC_XOR;
   input DC_ANDN;
   input [31:0] DC_B_Src1;
   input [31:0] DC_B_Src2;
   output[31:0] logical_out;
   reg    [31:0] logical_out;
always @(DC_B_Src1 or DC_B_Src2 or DC_AND or DC_OR or DC_XOR or DC_ANDN )
    begin
        logical_out=32'h0;
        if(DC_AND) begin
            logical_out=DC_B_Src1&DC_B_Src2;
          end
        if(DC_OR)  begin
            logical_out=DC_B_Src1|DC_B_Src2;
          end
        if(DC_XOR) begin
             logical_out=DC_B_Src1^DC_B_Src2;
          end
        if(DC_ANDN) begin
              logical_out=DC_B_Src1&(~DC_B_Src2);
          end
     end
endmodule