s_pack.v

verilog, TMSC6415 S单元代码

module S_PACK(DC_W_SPACK2,DC_W_SPACKU4,DC_B_Src2,DC_B_Src1,S_PACK_out);


input   DC_W_SPACK2;
input  DC_W_SPACKU4;
input [31:0] DC_B_Src2;
input [31:0] DC_B_Src1;
output [31:0] S_PACK_out;
          
//reg [31:0] S_PACK_out;
wire [31:0] S_PACK_out;
wire Src2_hight;
wire Src2_low;
wire Src1_hight;
wire Src1_low;
reg [31:0] SPACK2_out;
reg [31:0] SPACKU4_out; 
assign Src2_hight=(DC_B_Src2>32'h00007fff)&&(~DC_B_Src2[31]);
assign Src2_low=(DC_B_Src2<32'hFFFF8000)&&DC_B_Src2[31];


assign Src1_hight=(DC_B_Src1>32'h00007fff)&&(~DC_B_Src1[31]);
assign Src1_low=(DC_B_Src1<32'hFFFF8000)&&DC_B_Src1[31];
assign S_PACK_out=SPACK2_out | SPACKU4_out;

always@(DC_W_SPACK2 or DC_B_Src1 or DC_B_Src2 or Src2_hight or Src2_low or Src1_hight
          or Src1_low) 
 /*begin
    S_PACK_out[15:0]=DC_B_Src2[15:0];
    S_PACK_out[31:16]=DC_B_Src1[15:0];


          				

    if(!DC_W_SPACK2) S_PACK_out=32'h0;	 
    
     else if(DC_W_SPACK2) begin
      if (Src2_hight) S_PACK_out[15:0]=16'h7fff;
      else if (Src2_low) S_PACK_out[15:0]=16'h8000;
  
      if (Src1_hight) S_PACK_out[31:16]=16'h7fff;
      else if (Src1_low) S_PACK_out[31:16]=16'h8000;
    
    end		
     		      
 end*/
begin
   SPACK2_out=32'h0;
   if(DC_W_SPACK2) 
     begin
      if (Src2_hight) 
         SPACK2_out[15:0]=16'h7fff;
      else if (Src2_low) 
         SPACK2_out[15:0]=16'h8000; 
        else
         SPACK2_out[15:0]=DC_B_Src2[15:0];
      
      if (Src1_hight)
         SPACK2_out[31:16]=16'h7fff;
      else if (Src1_low)
         SPACK2_out[31:16]=16'h8000;   
        else
         SPACK2_out[31:16]=DC_B_Src1[15:0];
    end     
      
end
 
 always@(DC_W_SPACKU4 or DC_B_Src1 or DC_B_Src2)
 /*begin
    S_PACK_out[31:24]=DC_B_Src1[23:16];
    S_PACK_out[23:16]=DC_B_Src1[7:0];
    S_PACK_out[15:8]=DC_B_Src2[23:16];
    S_PACK_out[7:0]=DC_B_Src2[7:0];
    if(!DC_W_SPACKU4)         S_PACK_out=32'h0;
    else if(DC_W_SPACKU4) begin
      if ((DC_B_Src1[31:16]>16'h00ff)&&(~DC_B_Src1[31])) S_PACK_out[31:24]=8'hff;
      else if (DC_B_Src1[31]) S_PACK_out[31:24]=8'h00;

    if ((DC_B_Src1[15:0]>16'h00ff)&&(~DC_B_Src1[15])) S_PACK_out[23:16]=8'hff;
      else if (DC_B_Src1[15]) S_PACK_out[23:16]=8'h00;

      
    if ((DC_B_Src2[31:16]>16'h00ff)&&(~DC_B_Src2[31])) S_PACK_out[15:8]=8'hff;
      else if (DC_B_Src2[31]) S_PACK_out[15:8]=8'h00;
      
    if ((DC_B_Src2[15:0]>16'h00ff)&&(~DC_B_Src2[15])) S_PACK_out[7:0]=8'hff;
      else if (DC_B_Src2[15]) S_PACK_out[7:0]=8'h00;

    end
     
 end	*/
 begin
   SPACKU4_out=32'h0;
   if(DC_W_SPACKU4) 
     begin
      if ((DC_B_Src1[31:16]>16'h00ff)&&(~DC_B_Src1[31])) 
         SPACKU4_out[31:24]=8'hff;
      else if (DC_B_Src1[31]) 
         SPACKU4_out[31:24]=8'h00;
      else
         SPACKU4_out[31:24]=DC_B_Src1[23:16];
      
      if ((DC_B_Src1[15:0]>16'h00ff)&&(~DC_B_Src1[15])) 
         SPACKU4_out[23:16]=8'hff;
      else if (DC_B_Src1[15]) 
         SPACKU4_out[23:16]=8'h00;
      else
         SPACKU4_out[23:16]=DC_B_Src1[7:0];
         
      if ((DC_B_Src2[31:16]>16'h00ff)&&(~DC_B_Src2[31])) 
         SPACKU4_out[15:8]=8'hff;
      else if (DC_B_Src2[31]) 
         SPACKU4_out[15:8]=8'h00;
      else
         SPACKU4_out[15:8]=DC_B_Src2[23:16];
         
      if ((DC_B_Src2[15:0]>16'h00ff)&&(~DC_B_Src2[15])) 
         SPACKU4_out[7:0]=8'hff;
      else if (DC_B_Src2[15]) 
         SPACKU4_out[7:0]=8'h00;
      else
         SPACKU4_out[7:0]=DC_B_Src2[7:0];
      
     end   
 end
 
   
endmodule