s_bit.v

verilog, TMSC6415 S单元代码

`timescale 1ns/1ns

module S_bit ( 
	       			 SSHL_SHL,
               //SSHL_EXT,
               SSHL_SHL_EXT,
               SSHL_SHL_Src2Type,
               SHR_Src2Type_U,
               SHR_SSHL,
               SHR_Src2Type,
               EXT_DC_U ,   
               log_reg,
               use_result,
	       			 S_W_SAT, 
               S_B_UWrite_Data, 
               S_B_UWrite_Long_Data, 
               DC_B_Src2_Long,
               DC_CLR, 
               DC_EXT, 
               DC_SET, 
               DC_SHL, 
               DC_SHR, 
               DC_SSHL,
               //DC_Src2_Type,
               en_instruction_execute,
               DC_U, 
               DC_B_Src1, 
               DC_B_Src2, 
               bit_write_reg,
               bit_write_long_reg 
               //S_Use_Long_Addr,
               //DC_Invalid,
                );


input  SSHL_SHL,SSHL_SHL_EXT,SSHL_SHL_Src2Type,SHR_Src2Type,SHR_Src2Type_U,SHR_SSHL,EXT_DC_U,log_reg,use_result,DC_CLR, DC_EXT, DC_SET, DC_SHL, DC_SHR, DC_SSHL,
DC_U,en_instruction_execute;//DC_Invalid

input [31:0]  DC_B_Src2;
input [9:0]   DC_B_Src1;
input [7:0]   DC_B_Src2_Long;

output        S_W_SAT;
output        bit_write_long_reg;
output [31:0] S_B_UWrite_Data;
output [31:0] S_B_UWrite_Long_Data;

//output	      S_Use_Long_Addr;
output        bit_write_reg;

     

reg         	S_W_SAT;
reg  [31:0] 	dst_low_32;
reg  [7:0]  	long_dst;

//assign S_Use_Long_Addr=((DC_SHL||DC_SHR)&&DC_Src2_Type||(DC_SHL&&DC_U))&DC_Invalid;
//assign use_result=(DC_CLR||DC_EXT||DC_SET||DC_SHL||DC_SHR||DC_SSHL);
assign bit_write_reg=en_instruction_execute&&use_result;
assign bit_write_long_reg=en_instruction_execute&&log_reg;
assign S_B_UWrite_Long_Data={24'b0,long_dst};

wire [5:0] C_Lshifter;
wire [5:0] C_Rshifter;


assign C_Lshifter=(SSHL_SHL)?DC_B_Src1[5:0]:{1'b0,DC_B_Src1[9:5]};
//assign C_Rshifter=DC_SHR?DC_B_Src1[5:0]:(SSHL_EXT)?{1'b0,DC_B_Src1[4:0]}:{1'b0,~DC_B_Src1[4:0]};
assign C_Rshifter=(SHR_SSHL)?DC_B_Src1[5:0]:(DC_EXT)?{1'b0,DC_B_Src1[4:0]}:{1'b0,~DC_B_Src1[4:0]};

wire [39:0] Src_Lshiter;
wire [39:0] Src_Rshiter;

 
//assign 			Src_Lshiter[31:0]=(DC_SSHL||DC_SHL)?DC_B_Src2:32'hffffffff;
assign 			Src_Lshiter[31:0]=(SSHL_SHL_EXT)?DC_B_Src2:32'hffffffff;   //modify for ext 
assign 			Src_Lshiter[39:32]=(SSHL_SHL_Src2Type)?DC_B_Src2_Long:8'h0;
 
wire [39:0] Right_Shifter_Result;     
wire [39:0] Left_Shifter_Result;     


//assign 			Src_Rshiter[31:0]=DC_SHR?DC_B_Src2:32'hffffffff;
assign 			Src_Rshiter[31:0]=DC_SHR?DC_B_Src2:(DC_EXT?Left_Shifter_Result[31:0]:32'hffffffff);   //modify for ext 
//assign 			Src_Rshiter[39:32]=(DC_SHR&&DC_Src2_Type)?DC_B_Src2_Long:((DC_SHR&&!DC_Src2_Type&&!DC_U)?{8{DC_B_Src2[31]}}:8'h0);
assign 			Src_Rshiter[39:32]=(SHR_Src2Type)?DC_B_Src2_Long:((SHR_Src2Type_U)?{8{DC_B_Src2[31]}}:((EXT_DC_U)?{8{Left_Shifter_Result[31]}}:8'h0));
//如果SHR_Src2Type_U为一，即做32位的SHR时，高8位补 8{DC_B_Src2[31]} 



S_Right_Shifter R_shifter(
				.src (Src_Rshiter[39:0]),
				.count(C_Rshifter[5:0]),
				.unsign(DC_U),
				//.Src2_Type(DC_Src2_Type), 				//add for EXT
				.result(Right_Shifter_Result[39:0])
				);

S_Left_Shifter L_shifter(
				.src (Src_Lshiter[39:0]),
				.count(C_Lshifter[5:0]),
				.result(Left_Shifter_Result[39:0])
				);

wire [31:0] clr;
wire [31:0] set;

clr_set clr_set(
.Left_Shifter_Result(Left_Shifter_Result[31:0]),
.Right_Shifter_Result(Right_Shifter_Result[31:0]),
.src2(DC_B_Src2),
.clr(clr),
.set(set)
);

wire [31:0] dst_SSHL;
wire  SAT;

sshl sshl(
.Left_Shifter_Result(Left_Shifter_Result[31:0]),
.Right_Shifter_Result(Right_Shifter_Result[31:0]),
.DC_B_Src2(DC_B_Src2),
//.DC_B_Src1(DC_B_Src1),
.S_W_SAT(SAT),
.dst_SSHL(dst_SSHL),
.en_instruction_execute(en_instruction_execute)

);




/*
S_EXT EXT(
    .src     (DC_B_Src2),
    .csta    (DC_B_Src1[9:5]),
    .cstb    (DC_B_Src1[4:0]),
    .unsign  (DC_U),
    .result  (Ext_Result)
);  
*/

wire [31:0] S_B_UWrite_Data1;
assign S_B_UWrite_Data1=(DC_CLR||DC_SET ||DC_SHL ||DC_SHR||DC_SSHL)?dst_low_32:32'b0;
assign S_B_UWrite_Data=DC_EXT?Right_Shifter_Result[31:0]:S_B_UWrite_Data1;


//wire [31:0] Right_Shifter_16_Result;
always @(DC_B_Src1 or DC_B_Src2 or DC_B_Src2_Long or DC_U or clr or set or dst_SSHL or SAT
      or DC_CLR or DC_EXT or DC_SET or DC_SHL or DC_SHR or DC_SSHL 
      or Left_Shifter_Result or Right_Shifter_Result )
begin
  
  
  //dst_low_32=32'b0;
  long_dst=8'b0;
  S_W_SAT=1'b0;
  
  if(DC_CLR) begin
  
    dst_low_32=clr;
  end

  if(DC_SET) begin
    dst_low_32=set;
  end
 
  /*if(DC_EXT) begin
    dst_low_32=Right_Shifter_Result[31:0];		//modify for ext
  end */
 
  if(DC_SHL) begin
    {long_dst,dst_low_32}=Left_Shifter_Result;
  end
  
  if(DC_SHR) begin
    {long_dst,dst_low_32}=Right_Shifter_Result;
  end
  
  if(DC_SSHL) begin
  dst_low_32=dst_SSHL;
  S_W_SAT=SAT;
  end
  
  
  
  /*if(DC_SSHL) begin
    if(({1'b1,~Right_Shifter_Result[31:1]}&DC_B_Src2)==32'h0||({1'b0,Right_Shifter_Result[31:1]}|DC_B_Src2)==32'hffff_ffff) begin
    	dst_low_32=Left_Shifter_Result[31:0];
    	S_W_SAT=0;
    end else begin
      if(DC_B_Src2[31]) dst_low_32=32'h80000000;
      else dst_low_32=32'h7fffffff;
      S_W_SAT=en_instruction_execute;
    end
  end
*/
  
end

//C64 instruction  (SHR2,SHRU2)


/*S_Right_Shifter_16 Right_Shifter_16hign (
				.src (DC_B_Src2 [31:16]),
				.count(DC_B_Src1 [4:0]),
				.unsign(DC_U),
				.result(Right_Shifter_16_Result[31:16])
				);

S_Right_Shifter_16 Right_Shifter_16low (
				.src (DC_B_Src2 [15:0]),
				.count(DC_B_Src1 [4:0]),
				.unsign(DC_U),
				.result(Right_Shifter_16_Result[15:0])
				);*/

endmodule