dc_plus_s.v

verilog, TMSC6415 S单元代码

                    .use_result                (use_result),
                    .logic_use_result           (logic_use_result),
                    .clk                       (clk),
                    .reset                     (reset               ),                                                      
                    .stall                     (stall           ),
                    .DP_PCE1                   (DP_PCE1             ),
                    .DP_W_Sactive              (DP_W_Sactive        ),
                    .DP_B_Sfield               (DP_B_Sfield         ),
                    .DP_B_Smode                (DP_B_Smode          ),
                    .DC_W_Src2_Type            (DC_W_Src2_Type      ),
                    .DC_W_Z                    (DC_W_Z              ),
                    .DC_W_Condition_Exec       (DC_Condition_Exec ),
                    .DC_W_U                    (DC_W_U              ),                
                    .DC_SUB2                   (DC_SUB2             ),
                    .DC_SUB                    (DC_SUB              ),
                    .DC_SSHL                   (DC_SSHL             ),
                    .DC_SHR                    (DC_SHR              ),
                    .DC_SHL                    (DC_SHL              ),
                    .DC_SET                    (DC_SET              ),
                    .DC_BReg                   (DC_BReg             ),
                    .DC_OR                     (DC_OR               ),
                    .DC_XOR                    (DC_XOR              ),
                    .DC_MVKH                   (DC_MVKH             ),
                    .DC_MVC                    (DC_MVC              ),
                    .DC_EXT                    (DC_EXT              ),
                    .DC_MVK                    (DC_MVK              ),
                    .DC_CLR                    (DC_CLR              ),
                    .DC_BCst                   (DC_BCst             ),
                    .DC_AND                    (DC_AND              ),
                    .DC_ADD2                   (DC_ADD2             ),
                    .DC_ADD                    (DC_ADD              ),
                    .DC_SADD2                  (DC_SADD2            ),
                    .DC_SADD                   (DC_SADD             ),
                    .DC_SADDU4                 (DC_SADDU4           ),
                    .DC_SADDUS2                (DC_SADDUS2          ),
                    .DC_ADDKPC				         (DC_ADDKPC				    ),                    //c64
										.DC_BDEC                   (DC_BDEC             ),
										.DC_BPOS                   (DC_BPOS             ),
										.DC_BNOP_Cst               (DC_BNOP_Cst         ),
                    .DC_CMPEQ2                 (DC_CMPEQ2           ),
                    .DC_CMPEQ4                 (DC_CMPEQ4           ),
                    .DC_CMPGT2                 (DC_CMPGT2           ),
                    .DC_CMPGTU4                (DC_CMPGTU4          ),
                    .DC_PACKH2                 (DC_PACKH2           ),
                    .DC_PACKHL2                (DC_PACKHL2          ),
                    .DC_PACKLH2                (DC_PACKLH2          ),
                    //.DC_BNOP_Reg               (DC_BNOP_Reg         ),
                    .DC_UNPKHU4                (DC_UNPKHU4          ),
                    .DC_UNPKLU4                (DC_UNPKLU4          ),
                    .DC_ANDN                   (DC_ANDN             ),
                    .DC_PACK2                  (DC_PACK2            ),
                    .DC_SHLMB                  (DC_SHLMB            ),
                    .DC_SHRMB                  (DC_SHRMB            ),
                    .DC_SPACK2                 (DC_SPACK2           ),
                    .DC_SPACKU4                (DC_SPACKU4          ),
                    .DC_SHR2                   (DC_SHR2             ),
                    .DC_SHRU2	 				         (DC_SHRU2	 				  ),
                    .DC_B_Src1                 (DC_B_Src1           ),
                    .DC_B_Dst_Address          (DC_B_Dst_Address    ),         
                    .DC_W_Ssrc1re              (DC_W_Ssrc1re        ),
                    .DC_B_Ssrc1addr            (DC_B_Ssrc1addr      ),
                    .DC_B_Src2                 (DC_B_Src2           ),
                    .DC_W_Ssrc2re              (DC_W_Ssrc2re        ),
                    .DC_B_Ssrc2addr            (DC_B_Ssrc2addr      ),
                    .I_DC_W_TriSTre            (I_DC_W_TriSTre      ),
                    .I_DC_B_TriSTaddr          (I_DC_B_TriSTaddr    ),
                    .I_DC_W_TriCrossRE         (I_DC_W_TriCrossRE   ),        
                    .I_DC_B_TriCrossAddr       (I_DC_B_TriCrossAddr ),          
                    .DC_W_Scondre              (DC_W_Scondre        ),   
                    .DC_B_Scondaddr            (DC_B_Scondaddr      ),     
                   // .I_DC_W_BCst               (I_DC_W_BCst         ),  
		    					 //.I_DC_W_BReg               (I_DC_W_BReg         ), 
                    .DC_W_Sinvalid           (DC_W_Sinvalid     ),      
                    .DC_W_S_SWBP               (DC_W_S_SWBP         ), 
                    .PDC_con_Value             (PDC_con_Value       ), 
                    .Cst_BDEC                  (Cst_BDEC            ), 
                    .Ssrc1re                   (Ssrc1re             ),
                    .Ssrc2re                   (Ssrc2re             ),
                    .DC_W_TriCrossRE           (DC_W_TriCrossRE     ),
                    .DC_W_TriSTre              (DC_W_TriSTre        ),
                    .S_UBranch_Inst            (S_UBranch_Inst      ),
                    .DC_W_Src2inv              (DC_W_Src2inv),
                    .SUB_RE                    (SUB_RE)    
                   );
                   
                   
                   
wire [4:0]  S_B_UDst_Address;
wire [4:0]  S_B_UDst_Long_Address;
//wire        S_Use_Long_Addr;        //hcm added 2003-6-18

wire [31:0] S_B_UWrite_Data;
wire [31:0] S_B_UWrite_Long_Data;
wire        S_UBranch;
wire        S_UBranch_Inst;
wire        S_URead_Creg;
wire [4:0]  S_UCreg_Address;
wire        S_UWrite_Creg;
wire        S_UWrite_Long_Reg;
wire        S_UWrite_Reg;
wire        S_SNMIE;
wire        S_Interrupt_End;
wire        S_W_SAT;

wire                INT_DC_W_Sinvalid; //hcm added 2005-9-5
assign              INT_DC_W_Sinvalid=DC_W_Sinvalid&(!IH_W_INTEXEC);//hcm added 2005-9-5

S_Unit     S_Unit(
.DC_W_Src2inv                    (DC_W_Src2inv),
.DC_Condition_Exec               (DC_Condition_Exec     )    , 			// indicate the instruction is conditional execution
.DC_Z                            (DC_W_Z                  )    , 									// indicate the z bit
.CR_UZero                        (CR_UZero              )    , 							// come from register file, 1 when the conditional register is 0
.DC_B_Src1                       (DC_B_Src1             )    ,
.DC_Src2_Type                    (DC_W_Src2_Type          )    , 					// when process fixed point operation, 1 stands for long or creg( BReg or MVC)
.Cst_BDEC                        (Cst_BDEC              )    ,										//
.PCF                             (PCF                   )    ,										//
.DC_B_Src2                       (DC_B_Src2             )    ,
.DC_B_Dst_Address                (DC_B_Dst_Address      )    ,
.CtrlR_B_UData                   (CtrlR_B_UData         )    , 					// the data read from control register
.DC_W_U                          (DC_W_U                )    , 									// denote the operation is unsigned or signed, 1 stands for unsigned
.I_DC_W_Sinvalid                 (INT_DC_W_Sinvalid       )    ,
.DC_ADD                          (DC_ADD                )     ,
.DC_ADD2                         (DC_ADD2               )    ,
.DC_AND                          (DC_AND                )     ,
.DC_BCst                         (DC_BCst               )     ,
.DC_BReg                         (DC_BReg               )      ,
.DC_CLR                          (DC_CLR                )      ,
.DC_EXT                          (DC_EXT                )      ,
.DC_MVC                          (DC_MVC                )      ,
.DC_MVK                          (DC_MVK                )      ,
.DC_MVKH                         (DC_MVKH               )      ,
.DC_OR                           (DC_OR                 )       ,
.DC_SET                          (DC_SET                )       ,
.DC_SHL                          (DC_SHL                )       ,
.DC_SHR                          (DC_SHR                )       ,
.DC_SSHL                         (DC_SSHL               )       ,
.DC_SUB                          (DC_SUB                )       ,
.DC_SUB2                         (DC_SUB2               )        ,
.DC_XOR                          (DC_XOR                )       ,
.DC_SADD2                        (DC_SADD2              )       ,
.DC_SADD                         (DC_SADD               )       ,
.DC_SADDU4                       (DC_SADDU4             )        ,
.DC_SADDUS2                      (DC_SADDUS2            )        ,
.DC_ADDKPC                       (DC_ADDKPC             )        ,		
.DC_BDEC                         (DC_BDEC               )        ,      
.DC_BPOS                         (DC_BPOS               )        ,      
.DC_BNOP_Cst                     (DC_BNOP_Cst           )        ,  
.DC_CMPEQ2                       (DC_CMPEQ2             )        ,   
.DC_CMPEQ4                       (DC_CMPEQ4             )        ,   
.DC_CMPGT2                       (DC_CMPGT2             )        ,   
.DC_CMPGTU4                      (DC_CMPGTU4            )         ,  
.DC_PACKH2                       (DC_PACKH2             )         ,    
.DC_PACKHL2                      (DC_PACKHL2            )          ,   
.DC_PACKLH2                      (DC_PACKLH2            )          ,   
//.DC_BNOP_Reg                     (DC_BNOP_Reg           )        ,  
.DC_UNPKHU4                      (DC_UNPKHU4            )         ,    
.DC_UNPKLU4                      (DC_UNPKLU4            )         ,   
.DC_ANDN                         (DC_ANDN               )          ,                                     
.DC_PACK2                        (DC_PACK2              )           ,     
.DC_SHLMB                        (DC_SHLMB              )           ,     
.DC_SHRMB                        (DC_SHRMB              )           ,     
.DC_SPACK2                       (DC_SPACK2             )            ,    
.DC_SPACKU4                      (DC_SPACKU4            )          ,   
.DC_SHR2                         (DC_SHR2               )          ,      
.DC_SHRU2                        (DC_SHRU2              )          ,
.RF_B_ST                         (RF_B_ST               )            ,
.RF_B_S_src1                     (RF_B_S_src1           )            ,
.RF_B_S_src2                     (RF_B_S_src2           )            ,
.RF_B_CrossBarX                  (RF_B_CrossBarX        )            ,	 		
.stall                           (stall                 )             ,
//.clk                             (clk                   )              ,
//.reset                           (reset                 )            , 											// internal reset signal
.S_B_UDst_Address                (S_B_UDst_Address      )           , 					// the reg number need write to at E1 stage
.S_B_UDst_Long_Address           (S_B_UDst_Long_Address )           ,
.S_B_UWrite_Data                 (S_B_UWrite_Data       )           , 						// the data need written  at E1 stage
.S_B_UWrite_Long_Data            (S_B_UWrite_Long_Data  )            ,			  // the long data
.S_UBranch                       (S_UBranch             )           , 									// indicate there is a branch taken
.S_URead_Creg                    (S_URead_Creg          )           , 							// when a creg value is a source operand, then S unit read the creg itself
.S_UCreg_Address                 (S_UCreg_Address       )            ,
.S_UWrite_Creg                   (S_UWrite_Creg         )           , 							// the write control register signal of S unit at E1 stage
.S_UWrite_Long_Reg               (S_UWrite_Long_Reg     )           ,
.S_UWrite_Reg                    (S_UWrite_Reg          )            , 							// the write register signal of S unit
.S_SNMIE                         (S_SNMIE               )            ,
.S_Interrupt_End                 (S_Interrupt_End       )              ,
.S_W_SAT                         (S_W_SAT               )             ,
.Ssrc1re                         (Ssrc1re               )             ,
.Ssrc2re                         (Ssrc2re               )             ,
.DC_W_TriCrossRE                 (DC_W_TriCrossRE       )             ,
.DC_W_TriSTre                    (DC_W_TriSTre          )              ,
.SSHL_SHL                        (SSHL_SHL),
//.SSHL_EXT                        (SSHL_EXT),
.SSHL_SHL_EXT                     (SSHL_SHL_EXT),
.SSHL_SHL_Src2Type                (SSHL_SHL_Src2Type),
.SHR_Src2Type_U                   (SHR_Src2Type_U),
.SHR_SSHL                         (SHR_SSHL),
.SHR_Src2Type                     (SHR_Src2Type),
.EXT_DC_U                         (EXT_DC_U   ),
.log_reg                          (log_reg),
.use_result                       (use_result),
.logic_use_result                 (logic_use_result),
.SUB_RE                          (SUB_RE)
                    );

                   
                   
endmodule