dc_plus_s.v

verilog, TMSC6415 S单元代码

`timescale 1ns/10ps

module dc_plus_s(
                DP_udst_Sfield,
                DP_W_SBDECBPOS,
                IH_W_INTEXEC,  //  hcm added 2005-9-5
                clk,
                reset,
                crossbar_stall,
                D_W_Stall,
                DP_W_UMiss,
                RF_B_S_src1,
                RF_B_S_src2,
                RF_B_CrossBarX,
                RF_B_ST,
                DP_PCE1,
                DP_W_Sactive,
                DP_B_Sfield,
                DP_B_Smode,
                CR_UZero,
                CtrlR_B_UData,
                S_B_UDst_Address,
                S_B_UDst_Long_Address,
                PCF,								//split from   S_B_UWrite_Data for PCF
                S_B_UWrite_Data,
                S_B_UWrite_Long_Data,
                S_UBranch,
                S_UBranch_Inst,    //new signal for fetch 10.8
                S_URead_Creg,
                S_UCreg_Address,
                S_UWrite_Creg,
                S_UWrite_Long_Reg,
                S_UWrite_Reg,
                S_SNMIE,
                S_Interrupt_End,
                S_W_SAT,
                I_DC_W_TriSTre,
                I_DC_B_TriSTaddr,
                I_DC_W_TriCrossRE,
                I_DC_B_TriCrossAddr,
                DC_W_Scondre,
                DC_B_Scondaddr,
                DC_W_Ssrc1re,
                DC_B_Ssrc1addr,
                DC_W_Ssrc2re,
                DC_B_Ssrc2addr,
		          //  I_DC_W_Sinvalid,   //Add output ports for INT///
		            DC_W_S_SWBP,         // software bp decode add by liubw 2005-6-13
                PDC_con_Value        // real condition value  add by liubw 2005-6-13
                 );

input  [2:0]  DP_udst_Sfield;
input         DP_W_SBDECBPOS;
input         IH_W_INTEXEC;  //  hcm added 2005-9-5
input         clk;
input         reset;
        
input         D_W_Stall;
input         DP_W_UMiss;
input         crossbar_stall;

input[31:0]   RF_B_S_src1;
input[31:0]   RF_B_S_src2;
input[31:0]   RF_B_CrossBarX;
input[7:0]    RF_B_ST;
input [31:0]  DP_PCE1;
input         DP_W_Sactive;
input[25:0]   DP_B_Sfield;
input[2:0]    DP_B_Smode;
input         CR_UZero;
input [31:0]  CtrlR_B_UData;
input [3:0]   PDC_con_Value;

output [4:0]  S_B_UDst_Address;
output [4:0]  S_B_UDst_Long_Address;
//output        S_Use_Long_Addr;

output [31:0]	PCF;
output [31:0] S_B_UWrite_Data;
output [31:0] S_B_UWrite_Long_Data;
output        S_UBranch;
output        S_UBranch_Inst;
output        S_URead_Creg;
output [4:0]  S_UCreg_Address;
output        S_UWrite_Creg;
output        S_UWrite_Long_Reg;
output        S_UWrite_Reg;
output        S_SNMIE;
output        S_Interrupt_End;
output        S_W_SAT;

output        I_DC_W_TriSTre;
output[4:0]   I_DC_B_TriSTaddr;
output        I_DC_W_TriCrossRE;
output[4:0]   I_DC_B_TriCrossAddr;
output        DC_W_Scondre;
output[2:0]   DC_B_Scondaddr;
output        DC_W_Ssrc1re;
output[4:0]   DC_B_Ssrc1addr;
output        DC_W_Ssrc2re;
output[4:0]   DC_B_Ssrc2addr;
output        DC_W_S_SWBP;

///////////////////////////////////Add output ports for INT/////////////////////////////////
//output		I_DC_W_BCst;
//output		I_DC_W_BReg;
//output		I_DC_W_Sinvalid;
///////////////////////////////////END//////////////////////////////////////////////////////

wire        DC_W_Src2_Type;
wire        DC_W_Z;
wire        DC_Condition_Exec;
wire        DC_W_U;
wire        DC_SUB2;
wire        DC_SUB;
wire        DC_SSHL;
wire        DC_SHR;
wire        DC_SHL;
wire        DC_SET;
wire        DC_BReg;
wire        DC_OR;
wire        DC_XOR;
wire        DC_MVKH;
wire        DC_MVC;
wire        DC_EXT;
wire        DC_MVK;
wire        DC_CLR;
wire        DC_BCst;
wire        DC_AND;
wire        DC_ADD2;
wire        DC_ADD;
wire        DC_SADD2;
wire        DC_SADD;
wire        DC_SADDU4;
wire        DC_SADDUS2;

wire				DC_ADDKPC		;
wire				DC_BDEC     ;
wire				DC_BPOS     ;
wire				DC_BNOP_Cst ;
wire				DC_CMPEQ2   ;
wire				DC_CMPEQ4   ;
wire				DC_CMPGT2   ;
wire				DC_CMPGTU4  ;
wire				DC_PACKH2   ;
wire				DC_PACKHL2  ;
wire				DC_PACKLH2  ;
//wire				DC_BNOP_Reg ;
wire				DC_UNPKHU4  ;
wire				DC_UNPKLU4  ;
wire				DC_ANDN     ;
wire				DC_PACK2    ;
wire				DC_SHLMB    ;
wire				DC_SHRMB    ;
wire				DC_SPACK2   ;
wire				DC_SPACKU4  ;
wire				DC_SHR2     ;
wire				DC_SHRU2	 	;

wire[31:0]	Cst_BDEC;
wire[31:0]  DC_B_Src1;
wire[31:0]  DC_B_Src2;
wire[7:0]   DC_B_Src2_Long;
wire[4:0]   DC_B_Dst_Address;
wire        I_DC_W_Sinvalid;

wire        DC_W_Ssrc1re;
wire[4:0]   DC_B_Ssrc1addr;

wire        DC_W_Ssrc2re;
wire[4:0]   DC_B_Ssrc2addr;
wire        I_DC_W_TriSTre;
wire[4:0]   I_DC_B_TriSTaddr;
wire        I_DC_W_TriCrossRE;
wire[4:0]   I_DC_B_TriCrossAddr;
wire        DC_W_Scondre;
wire[2:0]   DC_B_Scondaddr;

wire [3:0]  PDC_con_Value;
wire        DC_W_S_SWBP;
wire        stall;
wire         SSHL_SHL_Src2Type;
wire          SSHL_SHL_EXT;
//wire          SSHL_EXT;
wire          SSHL_SHL;
wire          SHR_Src2Type_U;
wire          SHR_SSHL;
wire          SHR_Src2Type;
wire          EXT_DC_U;
wire          log_reg;
wire          use_result;
wire          logic_use_result;
assign   stall=DP_W_UMiss | crossbar_stall | D_W_Stall;


dc_s_decode  dc_s_decode(
                    .DP_udst_Sfield          (DP_udst_Sfield ),
                    .DP_W_SBDECBPOS             (DP_W_SBDECBPOS),
                    .SSHL_SHL_Src2Type       (SSHL_SHL_Src2Type),
                    .SSHL_SHL_EXT            (SSHL_SHL_EXT),
                    .SSHL_SHL                 (SSHL_SHL),
                    //.SSHL_EXT                 (SSHL_EXT),
                    .SHR_Src2Type_U               (SHR_Src2Type_U),
                    .SHR_SSHL                   (SHR_SSHL),
                    .SHR_Src2Type               (SHR_Src2Type),
                    .EXT_DC_U                   (EXT_DC_U   ),
                    .log_reg                   (log_reg),