s_math.v

verilog, TMSC6415 S单元代码

`timescale 1ns/10ps

module S_math (
	 							DC_B_Src1,
								DC_B_Src2,
								Cst_BDEC,
								DC_ADD,
								DC_BCst,
								DC_SUB,
								DC_SADD,
								DC_W_ADDKPC,
								DC_W_BDEC,
								DC_W_BPOS,
								DC_W_BNOP_Cst,
								S_B_UWrite_Data,
								math_PCF,
								en_instruction_execute,
								math_write_reg,
								math_branch,
								S_W_SAT
								);
input 				en_instruction_execute;
input [31:0]  DC_B_Src1;
input [31:0]  DC_B_Src2;
input [31:0]  Cst_BDEC;
input         DC_ADD;
input         DC_BCst;
input         DC_SUB;
input         DC_SADD;


input         DC_W_ADDKPC;     
input         DC_W_BDEC;       
input         DC_W_BPOS;       
input         DC_W_BNOP_Cst;   

output [31:0] S_B_UWrite_Data;
output [31:0] math_PCF;
output        math_write_reg;
output				math_branch;
output        S_W_SAT;

wire        BDEC_branch,BPOS_branch;
wire 				use_result;
wire [31:0] Adder_32_Result;
reg  [31:0] S_B_UWrite_Data;
reg  [31:0] pcf;   
reg         S_W_SAT;
assign use_result=(DC_ADD||DC_SUB||BDEC_branch||DC_SADD||DC_W_ADDKPC);
assign math_write_reg=en_instruction_execute&&use_result;
assign math_PCF=pcf; 				//跳转地址值
assign BDEC_branch=DC_W_BDEC&(!DC_B_Src2[31]);
//assign BDEC_ubranch=DC_W_BDEC&DC_B_Src2[31];

assign BPOS_branch=DC_W_BPOS&(!DC_B_Src2[31]);
assign math_branch=en_instruction_execute&&(DC_BCst||BDEC_branch||BPOS_branch||DC_W_BNOP_Cst);

always @(DC_B_Src1 or DC_B_Src2 or Cst_BDEC or DC_ADD or DC_BCst or DC_SUB or DC_SADD or DC_W_ADDKPC or  DC_W_BDEC or DC_W_BPOS or	DC_W_BNOP_Cst
      or Adder_32_Result or en_instruction_execute or BDEC_branch or BPOS_branch)
begin
  S_B_UWrite_Data=32'b0;
  pcf=32'b0;           
  S_W_SAT=1'b0;           
  if(DC_ADD || DC_SUB ||DC_W_ADDKPC)  S_B_UWrite_Data=Adder_32_Result;
  
  if( DC_BCst||DC_W_BNOP_Cst) pcf=Adder_32_Result;//跳转地址值

  if(BDEC_branch) 
		begin
		 pcf=Adder_32_Result;                       
		 S_B_UWrite_Data=DC_B_Src2-1;                       
		end
//	if (BDEC_ubranch) 
  //     S_B_UWrite_Data=DC_B_Src2;
 
	
  if(BPOS_branch)
      begin 
       pcf=Adder_32_Result;
      
       end 
 

  
   if(DC_SADD) //10.23  gongxiao add
   begin
      
      if(!DC_B_Src1[31]&&!DC_B_Src2[31]&&Adder_32_Result[31]) begin
            S_B_UWrite_Data=32'h7fffffff;
            S_W_SAT=1'b1;
          end
       else if (DC_B_Src1[31]&&DC_B_Src2[31]&&!Adder_32_Result[31]) begin
            S_B_UWrite_Data=32'h80000000;
            S_W_SAT=1'b1;
          end 
       else 
          begin
            S_B_UWrite_Data=Adder_32_Result;
            S_W_SAT=1'b0;
          end
       
     end  
end
//Src prepared for Bcst when decode  Src2<-PCE1<<5  Src1<-Cst

//wire [31:0] Src1;
wire [31:0] Src2;
 
//assign Src1=SUB_RE?DC_B_Src2[31:0]:DC_B_Src1[31:0];
//assign Src2=SUB_RE?DC_B_Src1[31:0]:DC_SUB?DC_B_Src2[31:0]:(DC_W_BDEC||DC_W_BPOS)?Cst_BDEC:DC_B_Src2[31:0];
//assign Src2=DC_SUB?DC_B_Src2[31:0]:(DC_W_BDEC||DC_W_BPOS)?Cst_BDEC:DC_B_Src2[31:0];
assign Src2=(DC_W_BDEC||DC_W_BPOS)?Cst_BDEC:DC_B_Src2[31:0];
S_Adder_32 adder_32(
           .A    (DC_B_Src1[31:0]),
           .B    (Src2[31:0]),
           .Cin  (DC_SUB),                                                                 
           .D    (Adder_32_Result),                                                        
           .Cout ()                                                                        
);

endmodule

//BDEC指令 DC_B_Src1为PCE1   DC_B_Src2为dst   Cst_BDEC为se(scst10)