s_right_shifter_16.v

verilog, TMSC6415 S单元代码

`timescale 1ns/10ps
/*
`timescale 1ns/10ps

module S_Right_Shifter_16(
src,
count,
unsign,
result
);

input [15:0] src;
input [4:0] count;
input unsign;
output [15:0] result;

reg  [15:0] result;

always @(unsign or src or count )
begin
  if(unsign) result=src>>count;
  else begin
    result={{16{src[15]}},src}>>count;
  end
end
endmodule
*/

module S_Right_Shifter_16(
src,
count,
unsign,
result
);

input [15:0] src;
input [4:0] count;
input unsign;
output [15:0] result;

reg  [15:0] result;


wire [4:0]count_1;
assign count_1=count[4]? 5'b01111: count;

always @(unsign or src or count_1 or count )
begin
  if(unsign) result=src>>count;
  else begin
    result={{16{src[15]}},src}>>count_1;
     
  end
end
endmodule