s_control.v

verilog, TMSC6415 S单元代码

`timescale 1ns/10ps

module S_Control(
DC_Condition_Exec,         // indicate the instruction is conditional execution
									         // 1 when the instruction is conditional;
                           // 0, when instruction is unconditional.
DC_Z,  						         // indicate the z bit
CR_UZero, 				         // come from register file, 1 when the conditional register is 0
DC_Invalid,
DC_Src2_Type,
DC_B_Dst_Address,
DC_B_Creg_Address,
syn_write_reg,
math_write_reg,
simd_write_reg,
bit_write_reg,
math_branch,
bit_write_long_reg,
logi_branch,
en_instruction_execute,
S_B_UDst_Address, 					// the reg number need write to at E1 stage
S_B_UDst_Long_Address,
S_UBranch, 									// indicate there is a branch taken
S_UCreg_Address,
S_UWrite_Long_Reg,
S_UWrite_Reg 								// the write register signal of S unit
);

input         DC_Condition_Exec;
input         DC_Z;
input         CR_UZero;
input         DC_Src2_Type;
input [4:0]   DC_B_Dst_Address;
input [4:0]   DC_B_Creg_Address;
input         DC_Invalid;
input         syn_write_reg;
input         math_write_reg;
input         simd_write_reg;
input         bit_write_reg;
input         bit_write_long_reg;
input         logi_branch;
input         math_branch;
output        en_instruction_execute;
output [4:0]  S_B_UDst_Address;
output [4:0]  S_B_UDst_Long_Address;
output        S_UBranch;
output [4:0]  S_UCreg_Address;
output        S_UWrite_Long_Reg;
output        S_UWrite_Reg;


assign en_instruction_execute=(!DC_Condition_Exec||!(DC_Z^CR_UZero))&&DC_Invalid;//指令执行时DC_Z为0、DC_Invalid为1

assign S_UWrite_Reg=syn_write_reg||math_write_reg||simd_write_reg||bit_write_reg;

assign S_B_UDst_Address=DC_B_Dst_Address;

assign S_UWrite_Long_Reg=bit_write_long_reg;
                     
//for simple, just change as DC_B_Dst_Address,
//invert the lowest bit to select high 32bits register in register pairs
assign S_B_UDst_Long_Address={DC_B_Dst_Address[4:1],1'b1};

//for simple,just change as DC_B_Dst_Address
assign S_UCreg_Address=DC_Src2_Type?DC_B_Creg_Address[4:0]:DC_B_Dst_Address;

//when no stall and (DC_BCst or DC_BReg),send branch and branch_pipe signal
//assign d_S_Branch=(en_instruction_execute&&(DC_BCst||DC_BReg))?1'b1:1'b0;
assign S_UBranch=logi_branch||math_branch;
endmodule