📄 dispselect.tan.rpt
字号:
+-------+----------------------------------+---------------------+---------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[0]~reg0 ; Q[0]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[1]~reg0 ; Q[0]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[2]~reg0 ; Q[0]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[0]~reg0 ; Q[1]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[1]~reg0 ; Q[1]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[2]~reg0 ; Q[1]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[0]~reg0 ; Q[2]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[1]~reg0 ; Q[2]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[2]~reg0 ; Q[2]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[0]~reg0 ; Q[3]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[1]~reg0 ; Q[3]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[2]~reg0 ; Q[3]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[0]~reg0 ; Q[4]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[1]~reg0 ; Q[4]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[2]~reg0 ; Q[4]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[0]~reg0 ; Q[5]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[1]~reg0 ; Q[5]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[2]~reg0 ; Q[5]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[0]~reg0 ; disp_select[2]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[1]~reg0 ; disp_select[2]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[2]~reg0 ; disp_select[2]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[0]~reg0 ; disp_select[1]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[1]~reg0 ; disp_select[1]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[2]~reg0 ; disp_select[1]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[0]~reg0 ; disp_select[0]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[1]~reg0 ; disp_select[0]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; disp_select[2]~reg0 ; disp_select[0]~reg0 ; clk ; clk ; None ; None ; 3.600 ns ;
+-------+----------------------------------+---------------------+---------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+---------------------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+---------------------+----------------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+---------------------+----------------+------------+
; N/A ; None ; 2.800 ns ; Q[0]~reg0 ; Q[0] ; clk ;
; N/A ; None ; 2.800 ns ; Q[1]~reg0 ; Q[1] ; clk ;
; N/A ; None ; 2.800 ns ; Q[2]~reg0 ; Q[2] ; clk ;
; N/A ; None ; 2.800 ns ; Q[3]~reg0 ; Q[3] ; clk ;
; N/A ; None ; 2.800 ns ; Q[4]~reg0 ; Q[4] ; clk ;
; N/A ; None ; 2.800 ns ; Q[5]~reg0 ; Q[5] ; clk ;
; N/A ; None ; 2.800 ns ; disp_select[2]~reg0 ; disp_select[2] ; clk ;
; N/A ; None ; 2.800 ns ; disp_select[1]~reg0 ; disp_select[1] ; clk ;
; N/A ; None ; 2.800 ns ; disp_select[0]~reg0 ; disp_select[0] ; clk ;
+-------+--------------+------------+---------------------+----------------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
Info: Processing started: Mon Jul 17 22:44:17 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off dispselect -c dispselect
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 175.44 MHz between source register "disp_select[0]~reg0" and destination register "Q[0]~reg0" (period= 5.7 ns)
Info: + Longest register to register delay is 3.600 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC11; Fanout = 13; REG Node = 'disp_select[0]~reg0'
Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC1; Fanout = 1; REG Node = 'Q[0]~reg0'
Info: Total cell delay = 2.600 ns ( 72.22 % )
Info: Total interconnect delay = 1.000 ns ( 27.78 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 1.300 ns
Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'clk'
Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC1; Fanout = 1; REG Node = 'Q[0]~reg0'
Info: Total cell delay = 1.300 ns ( 100.00 % )
Info: - Longest clock path from clock "clk" to source register is 1.300 ns
Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'clk'
Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC11; Fanout = 13; REG Node = 'disp_select[0]~reg0'
Info: Total cell delay = 1.300 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.300 ns
Info: + Micro setup delay of destination is 0.800 ns
Info: tco from clock "clk" to destination pin "Q[0]" through register "Q[0]~reg0" is 2.800 ns
Info: + Longest clock path from clock "clk" to source register is 1.300 ns
Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'clk'
Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC1; Fanout = 1; REG Node = 'Q[0]~reg0'
Info: Total cell delay = 1.300 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.300 ns
Info: + Longest register to pin delay is 0.200 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 1; REG Node = 'Q[0]~reg0'
Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'Q[0]'
Info: Total cell delay = 0.200 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Mon Jul 17 22:44:17 2006
Info: Elapsed time: 00:00:01
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