fenwei.v

用verillog HDL 写的数字频率计.在实验箱上测试通过

module fenwei(clk,dis,ledg,leds,ledb,op,Hz,ov);
	input 					clk;
	input 	[WIDTH - 1 : 0]	dis;
	output 	[3 : 0]			ledg,leds,ledb;
	output 	[2 : 0] 		op;
	output 					Hz;
	output					ov;
	
	reg 					Hz;
	reg 					ov;
	reg 	[3:0]			ledg,leds,ledb;
	reg 	[2:0] 			op;
	reg 	[WIDTH - 1 : 0] tmp;

	parameter WIDTH = 32;

	reg		[3 : 0]			led_tmp [5 : 0];
	reg 					state;
	reg		[2 : 0]			p;
	
	parameter 	STATE_IDLE = 1'b0,
				STATE_CONV = 1'b1;
	integer i;
	always @(posedge clk)
		begin
			case (state)
			STATE_IDLE:
				begin
					if(dis < 1000)// < 1K
					    begin
							Hz   <= 1'b1;
							ov   <= 1'b0;
						    ledg <= led_tmp[0];//选择分位后的个,十,百位
							leds <= led_tmp[1];
							ledb <= led_tmp[2];
						    op   <= 3'b000;
					    end
				    else if(dis < 10000) // < 10K
					    begin
							Hz   <= 1'b0;
							ov   <= 1'b0;
						    ledg <= led_tmp[1];//选分位后的十百,千
							leds <= led_tmp[2];
							ledb <= led_tmp[3];
						    op   <= 3'b100;//显示小数点在百位
					    end
				    else if(dis < 100000)// < 100K
					    begin
							Hz   <= 1'b0;
							ov   <= 1'b0;
						    ledg <= led_tmp[2];
							leds <= led_tmp[3];
							ledb <= led_tmp[4];
						    op   <= 3'b010;
					    end
				    else if(dis < 1000000) // < 1M
					    begin
						    Hz   <= 1'b0;
							ov   <= 1'b0;
						    ledg <= led_tmp[3];
							leds <= led_tmp[4];
							ledb <= led_tmp[5];
							op  <= 3'b001;
					    end
					else 
						begin //溢出
							Hz   <= 1'b0;
							ov   <= 1'b1;
							ledg <= 4'h9;
							leds <= 4'h9;
							ledb <= 4'h9;
							op   <= 3'b000;
						end
				
					tmp <= dis;
					p <= 0;
					for(i = 0;i < 5;i = i + 1)
						led_tmp[i] <= 4'h0;
					state <= STATE_CONV;
				end
			STATE_CONV:
				begin
					//转换结束条件,被除数为零或转换够6位
					if((p == 6) | (tmp == 0))
						begin
							state <= STATE_IDLE;
						end
					else
						begin
							led_tmp[p] <= tmp % 10;
							tmp <= tmp / 10;
							p <= p + 1;
						end
				end
			endcase
		end
endmodule