ddr_sdram.srr

DDR（双速率）SDRAM控制器参考设计verilog代码

$ Start of Compile
#Mon May 22 12:06:06 2000

Synplify Verilog Compiler, version 5.3.0, built Dec  7 1999
Copyright (C) 1994-1999, Synplicity Inc.  All Rights Reserved

@I::"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_sdram.v"
@I:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_sdram.v":"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\params.v"
@I::"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\params.v"
@I::"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\pll1.v"
@I::"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_control_interface.v"
@I:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_control_interface.v":"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\params.v"
@I::"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v"
@I:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\params.v"
@I::"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.v"
@I:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.v":"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\params.v"
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module ddr_sdram
Synthesizing module pll1
Synthesizing module ddr_control_interface
Synthesizing module ddr_command
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":111:32:111:37|No assignment to do_act
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":230:0:230:5|Ignoring missing reset value for signal oe4. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":230:0:230:5|Ignoring missing reset value for signal oe3. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":230:0:230:5|Optimizing register bit oe_shift[7] to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":278:0:278:5|Optimizing register bit rw_shift[3] to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":230:0:230:5|Optimizing register bit oe_shift[6] to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":278:0:278:5|Optimizing register bit rw_shift[2] to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":230:0:230:5|Optimizing register bit oe_shift[5] to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":230:0:230:5|Optimizing register bit oe_shift[4] to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":63:32:63:34|Input NOP is unused
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":69:32:69:36|Input SC_CL is unused
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":71:32:71:37|Input SC_RRD is unused
Synthesizing module ddr_data_path
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.v":80:32:80:36|No assignment to dqs3a
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.v":83:32:83:36|No assignment to dqs3b
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.v":100:32:100:39|No assignment to din2x_1a
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.v":196:0:196:5|Ignoring missing reset value for signal d2_OE. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.v":158:0:158:5|Ignoring missing reset value for signal din2a[31:0]. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.v":158:0:158:5|Ignoring missing reset value for signal dq2[15:0]. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.v":158:0:158:5|Ignoring missing reset value for signal dmin2a[3:0]. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.v":158:0:158:5|Feedback mux created for signal dm1[1:0]. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.v":109:0:109:5|Ignoring missing reset value for signal DATAOUT[31:0]. Did you forget the set/reset assignment for this signal?
Synthesizing module ddr_sdram
@END
Process took 0.4 seconds realtime, 0.42 seconds cputime
Synplify Altera Technology Mapper, version 5.3.0, built Dec  8 1999
Copyright (C) 1994-1998, Synplicity Inc.  All Rights Reserved
selecting ep20k400e
Reading constraint file: d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_sdram.sdc
Adding property syn_clock, value 10, to port CLK
Loading timing data for chip EP20K400E-1X
selecting ep20k400e
List of partitions to map:
selecting ep20k400e
   view:work.ddr_sdram(verilog)
Automatic dissolve at startup in view:work.ddr_sdram(verilog) of data_path4(ddr_data_path)
Automatic dissolve at startup in view:work.ddr_sdram(verilog) of data_path3(ddr_data_path)
Automatic dissolve at startup in view:work.ddr_sdram(verilog) of data_path2(ddr_data_path)
Automatic dissolve at startup in view:work.ddr_sdram(verilog) of data_path1(ddr_data_path)
@N:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_control_interface.v":228:0:228:5|Found counter in view:work.ddr_control_interface(verilog) inst timer[15:0]
Automatic dissolve during optimization of view:work.ddr_sdram(verilog) of control1(ddr_control_interface)
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_control_interface.v":106:0:106:5|Removing sequential instance control1.NOP of view:ALTERA.S_DFF(PRIM) because there are no references to its outputs 
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_control_interface.v":175:0:175:5|Removing sequential instance control1.SC_RRD[0] of view:ALTERA.S_DFFE(PRIM) because there are no references to its outputs 
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_control_interface.v":175:0:175:5|Removing sequential instance control1.SC_RRD[1] of view:ALTERA.S_DFFE(PRIM) because there are no references to its outputs 
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_control_interface.v":175:0:175:5|Removing sequential instance control1.SC_RRD[2] of view:ALTERA.S_DFFE(PRIM) because there are no references to its outputs 
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_control_interface.v":175:0:175:5|Removing sequential instance control1.SC_RRD[3] of view:ALTERA.S_DFFE(PRIM) because there are no references to its outputs 
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_control_interface.v":175:0:175:5|Removing sequential instance control1.SC_CL[1] of view:ALTERA.S_DFFE(PRIM) because there are no references to its outputs 
Loading timing data for chip EP20K400E-1X
selecting ep20k400e
Found clock CLK100_inferred_clock with period 5ns
Found clock CLK200_inferred_clock with period 5ns
Found clock CLK with period 10ns

		 ##### START TIMING REPORT #####
Set the Environment Variable SYNPLIFY_TIMING_REPORT_OLD to get the old timing report 


		 Performance Summary 
		*********************

                          Requested     Estimated     Requested     Estimated          
Clock                     Frequency     Frequency     Period        Period        Slack
---------------------------------------------------------------------------------------
CLK100_inferred_clock     200.0 MHz     94.3 MHz      5.0           10.6          -5.6 
CLK200_inferred_clock     200.0 MHz     116.3 MHz     5.0           8.6           -3.6 
=======================================================================================

		 Interface Information 
		***********************

Input Ports: 

Port            Reference                           User           Arrival     Required          
Name            Clock                               Constraint     Time        Time         Slack
-------------------------------------------------------------------------------------------------
ADDR[0]         CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
ADDR[1]         CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
ADDR[2]         CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
ADDR[3]         CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
ADDR[4]         CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
ADDR[5]         CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
ADDR[6]         CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
ADDR[7]         CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
ADDR[8]         CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
ADDR[9]         CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
ADDR[10]        CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
ADDR[11]        CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
ADDR[12]        CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
ADDR[13]        CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
ADDR[14]        CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
ADDR[15]        CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
ADDR[16]        CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
ADDR[17]        CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
ADDR[18]        CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
ADDR[19]        CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
ADDR[20]        CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
ADDR[21]        CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
CLK             System                              0.0            0.0         >2000.0      NA   
CMD[0]          CLK100_inferred_clock [rising]      0.0            0.0         -1.4         -1.4 
CMD[1]          CLK100_inferred_clock [rising]      0.0            0.0         -1.4         -1.4 
CMD[2]          CLK100_inferred_clock [rising]      0.0            0.0         -1.4         -1.4 
DATAIN[0]       CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
DATAIN[1]       CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
DATAIN[2]       CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
DATAIN[3]       CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
DATAIN[4]       CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
DATAIN[5]       CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
DATAIN[6]       CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
DATAIN[7]       CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
DATAIN[8]       CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
DATAIN[9]       CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
DATAIN[10]      CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
DATAIN[11]      CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
DATAIN[12]      CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
DATAIN[13]      CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
DATAIN[14]      CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
DATAIN[15]      CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
DATAIN[16]      CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4 
DATAIN[17]      CLK100_inferred_clock [rising]      0.0            0.0         -0.4         -0.4