ddr_sdram.srr
来自「DDR（双速率）SDRAM控制器参考设计verilog代码」· SRR 代码 · 共 714 行 · 第 1/5 页
SRR
714 行
DATAOUT[81] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[82] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[83] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[84] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[85] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[86] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[87] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[88] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[89] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[90] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[91] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[92] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[93] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[94] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[95] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[96] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[97] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[98] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[99] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[100] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[101] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[102] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[103] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[104] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[105] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[106] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[107] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[108] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[109] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[110] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[111] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[112] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[113] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[114] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[115] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[116] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[117] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[118] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[119] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[120] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[121] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[122] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[123] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[124] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[125] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[126] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[127] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DQM[0] CLK200_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DQM[1] CLK200_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DQM[2] CLK200_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DQM[3] CLK200_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DQM[4] CLK200_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DQM[5] CLK200_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DQM[6] CLK200_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DQM[7] CLK200_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DQS[0] CLK200_inferred_clock [falling] 0.0 5.9 5.0 -0.9
DQS[1] CLK200_inferred_clock [falling] 0.0 5.9 5.0 -0.9
DQS[2] CLK200_inferred_clock [falling] 0.0 5.9 5.0 -0.9
DQS[3] CLK200_inferred_clock [falling] 0.0 5.9 5.0 -0.9
DQS[4] CLK200_inferred_clock [falling] 0.0 5.9 5.0 -0.9
DQS[5] CLK200_inferred_clock [falling] 0.0 5.9 5.0 -0.9
DQS[6] CLK200_inferred_clock [falling] 0.0 5.9 5.0 -0.9
DQS[7] CLK200_inferred_clock [falling] 0.0 5.9 5.0 -0.9
DQ[0] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[1] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[2] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[3] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[4] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[5] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[6] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[7] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[8] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[9] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[10] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[11] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[12] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[13] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[14] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[15] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[16] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[17] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[18] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[19] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[20] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[21] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[22] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[23] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[24] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[25] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[26] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[27] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[28] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[29] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[30] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[31] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[32] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[33] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[34] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[35] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[36] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[37] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[38] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[39] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[40] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[41] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[42] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[43] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[44] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[45] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[46] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[47] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[48] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[49] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[50] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[51] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[52] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[53] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[54] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[55] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[56] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[57] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[58] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[59] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[60] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[61] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[62] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
DQ[63] CLK200_inferred_clock [falling] 0.0 8.4 5.0 -3.4
RAS_N CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
SA[0] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
SA[1] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
SA[2] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
SA[3] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
SA[4] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
SA[5] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
SA[6] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
SA[7] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
SA[8] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
SA[9] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
SA[10] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
SA[11] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
WE_N CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
==================================================================================================
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