ddr_sdram.srr
来自「DDR（双速率）SDRAM控制器参考设计verilog代码」· SRR 代码 · 共 714 行 · 第 1/5 页
SRR
714 行
DATAIN[18] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[19] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[20] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[21] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[22] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[23] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[24] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[25] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[26] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[27] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[28] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[29] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[30] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[31] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[32] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[33] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[34] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[35] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
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DATAIN[38] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[39] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
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DATAIN[42] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[43] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[44] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[45] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[46] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[47] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[48] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[49] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[50] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[51] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[52] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[53] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[54] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[55] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[56] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[57] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[58] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[59] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[60] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[61] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[62] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[63] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[64] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[65] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[66] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[67] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[68] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[69] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[70] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[71] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[72] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[73] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[74] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[75] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[76] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[77] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[78] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[79] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[80] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[81] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[82] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[83] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[84] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[85] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[86] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[87] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[88] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[89] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[90] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[91] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[92] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[93] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[94] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[95] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[96] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[97] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[98] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[99] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[100] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[101] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[102] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[103] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[104] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[105] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[106] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[107] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[108] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[109] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[110] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[111] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[112] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[113] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[114] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[115] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[116] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[117] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[118] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[119] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[120] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[121] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[122] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[123] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[124] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[125] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[126] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DATAIN[127] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DM[0] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DM[1] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DM[2] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DM[3] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DM[4] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DM[5] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DM[6] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DM[7] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DM[8] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DM[9] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DM[10] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DM[11] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DM[12] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DM[13] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DM[14] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DM[15] CLK100_inferred_clock [rising] 0.0 0.0 -0.4 -0.4
DQ[0] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[1] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[2] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[3] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[4] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[5] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[6] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[7] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[8] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[9] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[10] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[11] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[12] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[13] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[14] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[15] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[16] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
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