one.qsf

verilog设计的4位频率计

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		one_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY FLEX10K
set_global_assignment -name DEVICE "EPF10K10LC84-4"
set_global_assignment -name TOP_LEVEL_ENTITY one
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:36:30  JULY 15, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 7.2
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_global_assignment -name VERILOG_FILE count10.v
set_global_assignment -name VERILOG_FILE ctr.v
set_global_assignment -name VERILOG_FILE fp100HZ.v
set_global_assignment -name VERILOG_FILE fp50HZ.v
set_global_assignment -name VERILOG_FILE latch_16.v
set_global_assignment -name VERILOG_FILE ledout.v
set_global_assignment -name BDF_FILE one.bdf
set_location_assignment PIN_1 -to clk_50M
set_location_assignment PIN_2 -to clk2
set_location_assignment PIN_3 -to clr
set_location_assignment PIN_5 -to k1
set_location_assignment PIN_6 -to k2
set_location_assignment PIN_7 -to k3
set_location_assignment PIN_8 -to led_b[7]
set_location_assignment PIN_9 -to led_b[6]
set_location_assignment PIN_10 -to led_b[5]
set_location_assignment PIN_11 -to led_b[4]
set_location_assignment PIN_16 -to led_b[3]
set_location_assignment PIN_17 -to led_b[2]
set_location_assignment PIN_18 -to led_b[1]
set_location_assignment PIN_19 -to led_b[0]
set_location_assignment PIN_21 -to ledout[7]
set_location_assignment PIN_22 -to ledout[6]
set_location_assignment PIN_23 -to ledout[5]
set_location_assignment PIN_24 -to ledout[4]
set_location_assignment PIN_25 -to ledout[3]
set_location_assignment PIN_29 -to ledout[2]
set_location_assignment PIN_30 -to ledout[1]
set_location_assignment PIN_35 -to ledout[0]
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE AUTO
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL"
set_global_assignment -name VERILOG_FILE latch_8.v
set_global_assignment -name VERILOG_FILE fp4HZ.v
set_global_assignment -name VERILOG_FILE fp50000000HZ.v