one.map.summary

来自「verilog设计的4位频率计」· SUMMARY 代码 · 共 9 行

Analysis & Synthesis Status : Successful - Thu Jul 17 10:24:36 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : one
Top-level Entity Name : one
Family : FLEX10K
Total logic elements : 243
Total pins : 22
Total memory bits : 0