latch_16.v

来自「verilog设计的4位频率计」· Verilog 代码 · 共 9 行

module latch_16(qo,din,load);
output[27:0] qo;
input[27:0] din;
input load;//suocunxinhao
reg[27:0] qo;
always @(posedge load)
  begin qo=din;end
endmodule