one.map.rpt

verilog设计的4位频率计

; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                   ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                   ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                 ;
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Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


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; Analysis & Synthesis Messages ;
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Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu Jul 17 10:24:34 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off one -c one
Info: Found 1 design units, including 1 entities, in source file count10.v
    Info: Found entity 1: count10
Warning (10227): Verilog HDL Port Declaration warning at ctr.v(3): data type declaration for "gz2" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at ctr.v(6): "gz2" is declared here
Info: Found 1 design units, including 1 entities, in source file ctr.v
    Info: Found entity 1: ctr
Info: Found 1 design units, including 1 entities, in source file fp100HZ.v
    Info: Found entity 1: fp100HZ
Info: Found 1 design units, including 1 entities, in source file fp50HZ.v
    Info: Found entity 1: fp50HZ
Info: Found 1 design units, including 1 entities, in source file latch_16.v
    Info: Found entity 1: latch_16
Info: Found 1 design units, including 1 entities, in source file ledout.v
    Info: Found entity 1: ledout
Info: Found 1 design units, including 1 entities, in source file one.bdf
    Info: Found entity 1: one
Info: Found 1 design units, including 1 entities, in source file latch_8.v
    Info: Found entity 1: latch_8
Info: Found 1 design units, including 1 entities, in source file fp4HZ.v
    Info: Found entity 1: fp4HZ
Info: Found 1 design units, including 1 entities, in source file fp50000000HZ.v
    Info: Found entity 1: fp50000000HZ
Info: Elaborating entity "one" for the top level hierarchy
Info: Elaborating entity "ledout" for hierarchy "ledout:inst3"
Info: Elaborating entity "fp50HZ" for hierarchy "fp50HZ:inst11"
Warning (10230): Verilog HDL assignment warning at fp50HZ.v(12): truncated value with size 32 to match size of target (8)
Info: Elaborating entity "latch_16" for hierarchy "latch_16:inst2"
Info: Elaborating entity "ctr" for hierarchy "ctr:inst"
Info (10264): Verilog HDL Case Statement information at ctr.v(9): all case item expressions in this case statement are onehot
Info: Elaborating entity "fp50000000HZ" for hierarchy "fp50000000HZ:inst10"
Info: Elaborating entity "count10" for hierarchy "count10:inst1"
Warning (10230): Verilog HDL assignment warning at count10.v(15): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at count10.v(19): truncated value with size 32 to match size of target (1)
Warning (14130): Reduced register "ledout:inst3|b[24]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "ledout:inst3|b[25]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "ledout:inst3|b[26]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "ledout:inst3|b[27]" with stuck data_in port to stuck value GND
Info: Inferred 2 megafunctions from design logic
    Info: Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "fp50HZ:inst11|Add0"
    Info: Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "fp50000000HZ:inst10|Add0"
Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Elaborated megafunction instantiation "fp50HZ:inst11|lpm_add_sub:Add0"
Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Elaborated megafunction instantiation "fp50HZ:inst11|lpm_add_sub:Add0|addcore:adder", which is child of megafunction instantiation "fp50HZ:inst11|lpm_add_sub:Add0"
Info: Instantiated megafunction "fp50HZ:inst11|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "8"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Elaborated megafunction instantiation "fp50HZ:inst11|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "fp50HZ:inst11|lpm_add_sub:Add0"
Info: Instantiated megafunction "fp50HZ:inst11|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "8"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "fp50HZ:inst11|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "fp50HZ:inst11|lpm_add_sub:Add0"
Info: Instantiated megafunction "fp50HZ:inst11|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "8"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Elaborated megafunction instantiation "fp50HZ:inst11|lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "fp50HZ:inst11|lpm_add_sub:Add0"
Info: Instantiated megafunction "fp50HZ:inst11|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "8"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "fp50HZ:inst11|lpm_add_sub:Add0|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "fp50HZ:inst11|lpm_add_sub:Add0"
Info: Instantiated megafunction "fp50HZ:inst11|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "8"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "fp50000000HZ:inst10|lpm_add_sub:Add0"
Info: Elaborated megafunction instantiation "fp50000000HZ:inst10|lpm_add_sub:Add0|addcore:adder", which is child of megafunction instantiation "fp50000000HZ:inst10|lpm_add_sub:Add0"
Info: Instantiated megafunction "fp50000000HZ:inst10|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "32"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "fp50000000HZ:inst10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "fp50000000HZ:inst10|lpm_add_sub:Add0"
Info: Instantiated megafunction "fp50000000HZ:inst10|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "32"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "fp50000000HZ:inst10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "fp50000000HZ:inst10|lpm_add_sub:Add0"
Info: Instantiated megafunction "fp50000000HZ:inst10|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "32"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "fp50000000HZ:inst10|lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "fp50000000HZ:inst10|lpm_add_sub:Add0"
Info: Instantiated megafunction "fp50000000HZ:inst10|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "32"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Duplicate registers merged to single register
    Info: Duplicate register "ctr:inst|count_en" merged to single register "ctr:inst|load", power-up level changed
Info: Implemented 265 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 16 output pins
    Info: Implemented 243 logic cells
Info: Generated suppressed messages file D:/one/one.map.smsg
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
    Info: Allocated 141 megabytes of memory during processing
    Info: Processing ended: Thu Jul 17 10:24:36 2008
    Info: Elapsed time: 00:00:02


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; Analysis & Synthesis Suppressed Messages ;
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The suppressed messages can be found in D:/one/one.map.smsg.