one.tan.qmsg

verilog设计的4位频率计

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "39 " "Warning: Found 39 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "count10:inst1\|Equal0~57 " "Info: Detected gated clock \"count10:inst1\|Equal0~57\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 14 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst1\|Equal0~57" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "count10:inst5\|Equal0~57 " "Info: Detected gated clock \"count10:inst5\|Equal0~57\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 14 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst5\|Equal0~57" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "count10:inst4\|Equal0~57 " "Info: Detected gated clock \"count10:inst4\|Equal0~57\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 14 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst4\|Equal0~57" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "count10:inst6\|Equal0~57 " "Info: Detected gated clock \"count10:inst6\|Equal0~57\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 14 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst6\|Equal0~57" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "count10:inst8\|Equal0~57 " "Info: Detected gated clock \"count10:inst8\|Equal0~57\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 14 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst8\|Equal0~57" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "count10:inst7\|Equal0~57 " "Info: Detected gated clock \"count10:inst7\|Equal0~57\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 14 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst7\|Equal0~57" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "count10:inst5\|cout " "Info: Detected gated clock \"count10:inst5\|cout\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 3 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst5\|cout" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "count10:inst1\|cout " "Info: Detected gated clock \"count10:inst1\|cout\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 3 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst1\|cout" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "count10:inst4\|cout " "Info: Detected gated clock \"count10:inst4\|cout\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 3 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst4\|cout" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "count10:inst6\|cout " "Info: Detected gated clock \"count10:inst6\|cout\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 3 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst6\|cout" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "count10:inst8\|cout " "Info: Detected gated clock \"count10:inst8\|cout\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 3 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst8\|cout" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "count10:inst7\|cout " "Info: Detected gated clock \"count10:inst7\|cout\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 3 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst7\|cout" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst8\|out\[0\] " "Info: Detected ripple clock \"count10:inst8\|out\[0\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst8\|out\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst1\|out\[0\] " "Info: Detected ripple clock \"count10:inst1\|out\[0\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst1\|out\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst4\|out\[0\] " "Info: Detected ripple clock \"count10:inst4\|out\[0\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst4\|out\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst1\|out\[1\] " "Info: Detected ripple clock \"count10:inst1\|out\[1\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst1\|out\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst4\|out\[1\] " "Info: Detected ripple clock \"count10:inst4\|out\[1\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst4\|out\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst8\|out\[1\] " "Info: Detected ripple clock \"count10:inst8\|out\[1\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst8\|out\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst1\|out\[2\] " "Info: Detected ripple clock \"count10:inst1\|out\[2\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst1\|out\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst4\|out\[2\] " "Info: Detected ripple clock \"count10:inst4\|out\[2\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst4\|out\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst8\|out\[2\] " "Info: Detected ripple clock \"count10:inst8\|out\[2\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst8\|out\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst1\|out\[3\] " "Info: Detected ripple clock \"count10:inst1\|out\[3\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst1\|out\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst4\|out\[3\] " "Info: Detected ripple clock \"count10:inst4\|out\[3\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst4\|out\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst8\|out\[3\] " "Info: Detected ripple clock \"count10:inst8\|out\[3\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst8\|out\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst7\|out\[0\] " "Info: Detected ripple clock \"count10:inst7\|out\[0\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst7\|out\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst6\|out\[0\] " "Info: Detected ripple clock \"count10:inst6\|out\[0\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst6\|out\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst5\|out\[0\] " "Info: Detected ripple clock \"count10:inst5\|out\[0\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst5\|out\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst6\|out\[1\] " "Info: Detected ripple clock \"count10:inst6\|out\[1\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst6\|out\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst5\|out\[1\] " "Info: Detected ripple clock \"count10:inst5\|out\[1\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst5\|out\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst7\|out\[1\] " "Info: Detected ripple clock \"count10:inst7\|out\[1\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst7\|out\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst6\|out\[2\] " "Info: Detected ripple clock \"count10:inst6\|out\[2\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst6\|out\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst5\|out\[2\] " "Info: Detected ripple clock \"count10:inst5\|out\[2\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst5\|out\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst7\|out\[2\] " "Info: Detected ripple clock \"count10:inst7\|out\[2\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst7\|out\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst6\|out\[3\] " "Info: Detected ripple clock \"count10:inst6\|out\[3\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst6\|out\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst5\|out\[3\] " "Info: Detected ripple clock \"count10:inst5\|out\[3\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst5\|out\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "ctr:inst\|load " "Info: Detected ripple clock \"ctr:inst\|load\" as buffer" {  } { { "ctr.v" "" { Text "D:/one/ctr.v" 2 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "ctr:inst\|load" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count10:inst7\|out\[3\] " "Info: Detected ripple clock \"count10:inst7\|out\[3\]\" as buffer" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count10:inst7\|out\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "fp50000000HZ:inst10\|clkout " "Info: Detected ripple clock \"fp50000000HZ:inst10\|clkout\" as buffer" {  } { { "fp50000000HZ.v" "" { Text "D:/one/fp50000000HZ.v" 3 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "fp50000000HZ:inst10\|clkout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "fp50HZ:inst11\|clkout " "Info: Detected ripple clock \"fp50HZ:inst11\|clkout\" as buffer" {  } { { "fp50HZ.v" "" { Text "D:/one/fp50HZ.v" 3 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "fp50HZ:inst11\|clkout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_50M register count10:inst9\|out\[1\] register latch_16:inst2\|qo\[25\] 15.2 MHz 65.8 ns Internal " "Info: Clock \"clk_50M\" has Internal fmax of 15.2 MHz between source register \"count10:inst9\|out\[1\]\" and destination register \"latch_16:inst2\|qo\[25\]\" (period= 65.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.400 ns + Longest register register " "Info: + Longest register to register delay is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count10:inst9\|out\[1\] 1 REG LC2_A14 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_A14; Fanout = 5; REG Node = 'count10:inst9\|out\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { count10:inst9|out[1] } "NODE_NAME" } } { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.200 ns) 3.400 ns latch_16:inst2\|qo\[25\] 2 REG LC7_A13 1 " "Info: 2: + IC(2.200 ns) + CELL(1.200 ns) = 3.400 ns; Loc. = LC7_A13; Fanout = 1; REG Node = 'latch_16:inst2\|qo\[25\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { count10:inst9|out[1] latch_16:inst2|qo[25] } "NODE_NAME" } } { "latch_16.v" "" { Text "D:/one/latch_16.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns ( 35.29 % ) " "Info: Total cell delay = 1.200 ns ( 35.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns ( 64.71 % ) " "Info: Total interconnect delay = 2.200 ns ( 64.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { count10:inst9|out[1] latch_16:inst2|qo[25] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.400 ns" { count10:inst9|out[1] {} latch_16:inst2|qo[25] {} } { 0.000ns 2.200ns } { 0.000ns 1.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-58.800 ns - Smallest " "Info: - Smallest clock skew is -58.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50M destination 15.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_50M\" to destination register is 15.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk_50M 1 CLK PIN_1 42 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_1; Fanout = 42; CLK Node = 'clk_50M'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50M } "NODE_NAME" } } { "one.bdf" "" { Schematic "D:/one/one.bdf" { { 80 160 328 96 "clk_50M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns fp50000000HZ:inst10\|clkout 2 REG LC8_A3 5 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC8_A3; Fanout = 5; REG Node = 'fp50000000HZ:inst10\|clkout'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { clk_50M fp50000000HZ:inst10|clkout } "NODE_NAME" } } { "fp50000000HZ.v" "" { Text "D:/one/fp50000000HZ.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.100 ns) 9.900 ns ctr:inst\|load 3 REG LC2_A6 37 " "Info: 3: + IC(2.400 ns) + CELL(1.100 ns) = 9.900 ns; Loc. = LC2_A6; Fanout = 37; REG Node = 'ctr:inst\|load'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { fp50000000HZ:inst10|clkout ctr:inst|load } "NODE_NAME" } } { "ctr.v" "" { Text "D:/one/ctr.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.500 ns) + CELL(0.000 ns) 15.400 ns latch_16:inst2\|qo\[25\] 4 REG LC7_A13 1 " "Info: 4: + IC(5.500 ns) + CELL(0.000 ns) = 15.400 ns; Loc. = LC7_A13; Fanout = 1; REG Node = 'latch_16:inst2\|qo\[25\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { ctr:inst|load latch_16:inst2|qo[25] } "NODE_NAME" } } { "latch_16.v" "" { Text "D:/one/latch_16.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 32.47 % ) " "Info: Total cell delay = 5.000 ns ( 32.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.400 ns ( 67.53 % ) " "Info: Total interconnect delay = 10.400 ns ( 67.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.400 ns" { clk_50M fp50000000HZ:inst10|clkout ctr:inst|load latch_16:inst2|qo[25] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "15.400 ns" { clk_50M {} clk_50M~out {} fp50000000HZ:inst10|clkout {} ctr:inst|load {} latch_16:inst2|qo[25] {} } { 0.000ns 0.000ns 2.500ns 2.400ns 5.500ns } { 0.000ns 2.800ns 1.100ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50M source 74.200 ns - Longest register " "Info: - Longest clock path from clock \"clk_50M\" to source register is 74.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk_50M 1 CLK PIN_1 42 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_1; Fanout = 42; CLK Node = 'clk_50M'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50M } "NODE_NAME" } } { "one.bdf" "" { Schematic "D:/one/one.bdf" { { 80 160 328 96 "clk_50M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns fp50000000HZ:inst10\|clkout 2 REG LC8_A3 5 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC8_A3; Fanout = 5; REG Node = 'fp50000000HZ:inst10\|clkout'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { clk_50M fp50000000HZ:inst10|clkout } "NODE_NAME" } } { "fp50000000HZ.v" "" { Text "D:/one/fp50000000HZ.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.100 ns) 9.900 ns ctr:inst\|load 3 REG LC2_A6 37 " "Info: 3: + IC(2.400 ns) + CELL(1.100 ns) = 9.900 ns; Loc. = LC2_A6; Fanout = 37; REG Node = 'ctr:inst\|load'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { fp50000000HZ:inst10|clkout ctr:inst|load } "NODE_NAME" } } { "ctr.v" "" { Text "D:/one/ctr.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.400 ns) + CELL(2.300 ns) 18.600 ns count10:inst1\|cout 4 COMB LC1_A24 4 " "Info: 4: + IC(6.400 ns) + CELL(2.300 ns) = 18.600 ns; Loc. = LC1_A24; Fanout = 4; COMB Node = 'count10:inst1\|cout'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.700 ns" { ctr:inst|load count10:inst1|cout } "NODE_NAME" } } { "count10.v" "" { Text "D:/one/count10.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(1.100 ns) 22.600 ns count10:inst4\|out\[0\] 5 REG LC7_A1 6 " "Info: 5: + IC(2.900 ns) + CELL(1.100 ns) = 22.600 ns; Loc. = LC7_A1; Fanout = 6; REG Node = 'count10:inst4\|out\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { count10:inst1|cout count10:inst4|out[0] } "NODE_NAME" } } { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 25.500 ns count10:inst4\|Equal0~57 6 COMB LC5_A1 2 " "Info: 6: + IC(0.600 ns) + CELL(2.300 ns) = 25.500 ns; Loc. = LC5_A1; Fanout = 2; COMB Node = 'count10:inst4\|Equal0~57'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { count10:inst4|out[0] count10:inst4|Equal0~57 } "NODE_NAME" } } { "count10.v" "" { Text "D:/one/count10.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.800 ns) 29.600 ns count10:inst4\|cout 7 COMB LC4_A4 4 " "Info: 7: + IC(2.300 ns) + CELL(1.800 ns) = 29.600 ns; Loc. = LC4_A4; Fanout = 4; COMB Node = 'count10:inst4\|cout'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.100 ns" { count10:inst4|Equal0~57 count10:inst4|cout } "NODE_NAME" } } { "count10.v" "" { Text "D:/one/count10.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.100 ns) 33.000 ns count10:inst5\|out\[0\] 8 REG LC7_A9 6 " "Info: 8: + IC(2.300 ns) + CELL(1.100 ns) = 33.000 ns; Loc. = LC7_A9; Fanout = 6; REG Node = 'count10:inst5\|out\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { count10:inst4|cout count10:inst5|out[0] } "NODE_NAME" } } { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 35.900 ns count10:inst5\|Equal0~57 9 COMB LC5_A9 2 " "Info: 9: + IC(0.600 ns) + CELL(2.300 ns) = 35.900 ns; Loc. = LC5_A9; Fanout = 2; COMB Node = 'count10:inst5\|Equal0~57'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { count10:inst5|out[0] count10:inst5|Equal0~57 } "NODE_NAME" } } { "count10.v" "" { Text "D:/one/count10.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 39.900 ns count10:inst5\|cout 10 COMB LC2_A7 4 " "Info: 10: + IC(2.200 ns) + CELL(1.800 ns) = 39.900 ns; Loc. = LC2_A7; Fanout = 4; COMB Node = 'count10:inst5\|cout'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { count10:inst5|Equal0~57 count10:inst5|cout } "NODE_NAME" } } { "count10.v" "" { Text "D:/one/count10.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.100 ns) 43.700 ns count10:inst6\|out\[0\] 11 REG LC7_A17 6 " "Info: 11: + IC(2.700 ns) + CELL(1.100 ns) = 43.700 ns; Loc. = LC7_A17; Fanout = 6; REG Node = 'count10:inst6\|out\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { count10:inst5|cout count10:inst6|out[0] } "NODE_NAME" } } { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 46.600 ns count10:inst6\|Equal0~57 12 COMB LC5_A17 2 " "Info: 12: + IC(0.600 ns) + CELL(2.300 ns) = 46.600 ns; Loc. = LC5_A17; Fanout = 2; COMB Node = 'count10:inst6\|Equal0~57'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { count10:inst6|out[0] count10:inst6|Equal0~57 } "NODE_NAME" } } { "count10.v" "" { Text "D:/one/count10.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 50.600 ns count10:inst6\|cout 13 COMB LC2_A23 4 " "Info: 13: + IC(2.200 ns) + CELL(1.800 ns) = 50.600 ns; Loc. = LC2_A23; Fanout = 4; COMB Node = 'count10:inst6\|cout'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { count10:inst6|Equal0~57 count10:inst6|cout } "NODE_NAME" } } { "count10.v" "" { Text "D:/one/count10.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(1.100 ns) 54.300 ns count10:inst7\|out\[0\] 14 REG LC7_A19 6 " "Info: 14: + IC(2.600 ns) + CELL(1.100 ns) = 54.300 ns; Loc. = LC7_A19; Fanout = 6; REG Node = 'count10:inst7\|out\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { count10:inst6|cout count10:inst7|out[0] } "NODE_NAME" } } { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 57.200 ns count10:inst7\|Equal0~57 15 COMB LC5_A19 2 " "Info: 15: + IC(0.600 ns) + CELL(2.300 ns) = 57.200 ns; Loc. = LC5_A19; Fanout = 2; COMB Node = 'count10:inst7\|Equal0~57'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { count10:inst7|out[0] count10:inst7|Equal0~57 } "NODE_NAME" } } { "count10.v" "" { Text "D:/one/count10.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(1.800 ns) 61.600 ns count10:inst7\|cout 16 COMB LC4_A24 4 " "Info: 16: + IC(2.600 ns) + CELL(1.800 ns) = 61.600 ns; Loc. = LC4_A24; Fanout = 4; COMB Node = 'count10:inst7\|cout'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { count10:inst7|Equal0~57 count10:inst7|cout } "NODE_NAME" } } { "count10.v" "" { Text "D:/one/count10.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.100 ns) 64.900 ns count10:inst8\|out\[0\] 17 REG LC7_A16 6 " "Info: 17: + IC(2.200 ns) + CELL(1.100 ns) = 64.900 ns; Loc. = LC7_A16; Fanout = 6; REG Node = 'count10:inst8\|out\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.300 ns" { count10:inst7|cout count10:inst8|out[0] } "NODE_NAME" } } { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 67.800 ns count10:inst8\|Equal0~57 18 COMB LC5_A16 2 " "Info: 18: + IC(0.600 ns) + CELL(2.300 ns) = 67.800 ns; Loc. = LC5_A16; Fanout = 2; COMB Node = 'count10:inst8\|Equal0~57'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { count10:inst8|out[0] count10:inst8|Equal0~57 } "NODE_NAME" } } { "count10.v" "" { Text "D:/one/count10.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.800 ns) 71.900 ns count10:inst8\|cout 19 COMB LC8_A23 4 " "Info: 19: + IC(2.300 ns) + CELL(1.800 ns) = 71.900 ns; Loc. = LC8_A23; Fanout = 4; COMB Node = 'count10:inst8\|cout'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.100 ns" { count10:inst8|Equal0~57 count10:inst8|cout } "NODE_NAME" } } { "count10.v" "" { Text "D:/one/count10.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(0.000 ns) 74.200 ns count10:inst9\|out\[1\] 20 REG LC2_A14 5 " "Info: 20: + IC(2.300 ns) + CELL(0.000 ns) = 74.200 ns; Loc. = LC2_A14; Fanout = 5; REG Node = 'count10:inst9\|out\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { count10:inst8|cout count10:inst9|out[1] } "NODE_NAME" } } { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "33.300 ns ( 44.88 % ) " "Info: Total cell delay = 33.300 ns ( 44.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "40.900 ns ( 55.12 % ) " "Info: Total interconnect delay = 40.900 ns ( 55.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "74.200 ns" { clk_50M fp50000000HZ:inst10|clkout ctr:inst|load count10:inst1|cout count10:inst4|out[0] count10:inst4|Equal0~57 count10:inst4|cout count10:inst5|out[0] count10:inst5|Equal0~57 count10:inst5|cout count10:inst6|out[0] count10:inst6|Equal0~57 count10:inst6|cout count10:inst7|out[0] count10:inst7|Equal0~57 count10:inst7|cout count10:inst8|out[0] count10:inst8|Equal0~57 count10:inst8|cout count10:inst9|out[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "74.200 ns" { clk_50M {} clk_50M~out {} fp50000000HZ:inst10|clkout {} ctr:inst|load {} count10:inst1|cout {} count10:inst4|out[0] {} count10:inst4|Equal0~57 {} count10:inst4|cout {} count10:inst5|out[0] {} count10:inst5|Equal0~57 {} count10:inst5|cout {} count10:inst6|out[0] {} count10:inst6|Equal0~57 {} count10:inst6|cout {} count10:inst7|out[0] {} count10:inst7|Equal0~57 {} count10:inst7|cout {} count10:inst8|out[0] {} count10:inst8|Equal0~57 {} count10:inst8|cout {} count10:inst9|out[1] {} } { 0.000ns 0.000ns 2.500ns 2.400ns 6.400ns 2.900ns 0.600ns 2.300ns 2.300ns 0.600ns 2.200ns 2.700ns 0.600ns 2.200ns 2.600ns 0.600ns 2.600ns 2.200ns 0.600ns 2.300ns 2.300ns } { 0.000ns 2.800ns 1.100ns 1.100ns 2.300ns 1.100ns 2.300ns 1.800ns 1.100ns 2.300ns 1.800ns 1.100ns 2.300ns 1.800ns 1.100ns 2.300ns 1.800ns 1.100ns 2.300ns 1.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.400 ns" { clk_50M fp50000000HZ:inst10|clkout ctr:inst|load latch_16:inst2|qo[25] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "15.400 ns" { clk_50M {} clk_50M~out {} fp50000000HZ:inst10|clkout {} ctr:inst|load {} latch_16:inst2|qo[25] {} } { 0.000ns 0.000ns 2.500ns 2.400ns 5.500ns } { 0.000ns 2.800ns 1.100ns 1.100ns 0.000ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "74.200 ns" { clk_50M fp50000000HZ:inst10|clkout ctr:inst|load count10:inst1|cout count10:inst4|out[0] count10:inst4|Equal0~57 count10:inst4|cout count10:inst5|out[0] count10:inst5|Equal0~57 count10:inst5|cout count10:inst6|out[0] count10:inst6|Equal0~57 count10:inst6|cout count10:inst7|out[0] count10:inst7|Equal0~57 count10:inst7|cout count10:inst8|out[0] count10:inst8|Equal0~57 count10:inst8|cout count10:inst9|out[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "74.200 ns" { clk_50M {} clk_50M~out {} fp50000000HZ:inst10|clkout {} ctr:inst|load {} count10:inst1|cout {} count10:inst4|out[0] {} count10:inst4|Equal0~57 {} count10:inst4|cout {} count10:inst5|out[0] {} count10:inst5|Equal0~57 {} count10:inst5|cout {} count10:inst6|out[0] {} count10:inst6|Equal0~57 {} count10:inst6|cout {} count10:inst7|out[0] {} count10:inst7|Equal0~57 {} count10:inst7|cout {} count10:inst8|out[0] {} count10:inst8|Equal0~57 {} count10:inst8|cout {} count10:inst9|out[1] {} } { 0.000ns 0.000ns 2.500ns 2.400ns 6.400ns 2.900ns 0.600ns 2.300ns 2.300ns 0.600ns 2.200ns 2.700ns 0.600ns 2.200ns 2.600ns 0.600ns 2.600ns 2.200ns 0.600ns 2.300ns 2.300ns } { 0.000ns 2.800ns 1.100ns 1.100ns 2.300ns 1.100ns 2.300ns 1.800ns 1.100ns 2.300ns 1.800ns 1.100ns 2.300ns 1.800ns 1.100ns 2.300ns 1.800ns 1.100ns 2.300ns 1.800ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "count10.v" "" { Text "D:/one/count10.v" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "latch_16.v" "" { Text "D:/one/latch_16.v" 6 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { count10:inst9|out[1] latch_16:inst2|qo[25] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.400 ns" { count10:inst9|out[1] {} latch_16:inst2|qo[25] {} } { 0.000ns 2.200ns } { 0.000ns 1.200ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.400 ns" { clk_50M fp50000000HZ:inst10|clkout ctr:inst|load latch_16:inst2|qo[25] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "15.400 ns" { clk_50M {} clk_50M~out {} fp50000000HZ:inst10|clkout {} ctr:inst|load {} latch_16:inst2|qo[25] {} } { 0.000ns 0.000ns 2.500ns 2.400ns 5.500ns } { 0.000ns 2.800ns 1.100ns 1.100ns 0.000ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "74.200 ns" { clk_50M fp50000000HZ:inst10|clkout ctr:inst|load count10:inst1|cout count10:inst4|out[0] count10:inst4|Equal0~57 count10:inst4|cout count10:inst5|out[0] count10:inst5|Equal0~57 count10:inst5|cout count10:inst6|out[0] count10:inst6|Equal0~57 count10:inst6|cout count10:inst7|out[0] count10:inst7|Equal0~57 count10:inst7|cout count10:inst8|out[0] count10:inst8|Equal0~57 count10:inst8|cout count10:inst9|out[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "74.200 ns" { clk_50M {} clk_50M~out {} fp50000000HZ:inst10|clkout {} ctr:inst|load {} count10:inst1|cout {} count10:inst4|out[0] {} count10:inst4|Equal0~57 {} count10:inst4|cout {} count10:inst5|out[0] {} count10:inst5|Equal0~57 {} count10:inst5|cout {} count10:inst6|out[0] {} count10:inst6|Equal0~57 {} count10:inst6|cout {} count10:inst7|out[0] {} count10:inst7|Equal0~57 {} count10:inst7|cout {} count10:inst8|out[0] {} count10:inst8|Equal0~57 {} count10:inst8|cout {} count10:inst9|out[1] {} } { 0.000ns 0.000ns 2.500ns 2.400ns 6.400ns 2.900ns 0.600ns 2.300ns 2.300ns 0.600ns 2.200ns 2.700ns 0.600ns 2.200ns 2.600ns 0.600ns 2.600ns 2.200ns 0.600ns 2.300ns 2.300ns } { 0.000ns 2.800ns 1.100ns 1.100ns 2.300ns 1.100ns 2.300ns 1.800ns 1.100ns 2.300ns 1.800ns 1.100ns 2.300ns 1.800ns 1.100ns 2.300ns 1.800ns 1.100ns 2.300ns 1.800ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}