prev_cmp_one.map.qmsg

verilog设计的4位频率计

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "latch_16 latch_16:inst2 " "Info: Elaborating entity \"latch_16\" for hierarchy \"latch_16:inst2\"" {  } { { "one.bdf" "inst2" { Schematic "D:/one/one.bdf" { { 432 888 1032 528 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ctr ctr:inst " "Info: Elaborating entity \"ctr\" for hierarchy \"ctr:inst\"" {  } { { "one.bdf" "inst" { Schematic "D:/one/one.bdf" { { 392 408 520 520 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "ctr.v(9) " "Info (10264): Verilog HDL Case Statement information at ctr.v(9): all case item expressions in this case statement are onehot" {  } { { "ctr.v" "" { Text "D:/one/ctr.v" 9 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fp50000000HZ fp50000000HZ:inst10 " "Info: Elaborating entity \"fp50000000HZ\" for hierarchy \"fp50000000HZ:inst10\"" {  } { { "one.bdf" "inst10" { Schematic "D:/one/one.bdf" { { 240 168 264 336 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "count10 count10:inst1 " "Info: Elaborating entity \"count10\" for hierarchy \"count10:inst1\"" {  } { { "one.bdf" "inst1" { Schematic "D:/one/one.bdf" { { 16 680 792 112 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 count10.v(15) " "Warning (10230): Verilog HDL assignment warning at count10.v(15): truncated value with size 32 to match size of target (4)" {  } { { "count10.v" "" { Text "D:/one/count10.v" 15 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 count10.v(19) " "Warning (10230): Verilog HDL assignment warning at count10.v(19): truncated value with size 32 to match size of target (1)" {  } { { "count10.v" "" { Text "D:/one/count10.v" 19 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ledout:inst3\|b\[24\] data_in GND " "Warning (14130): Reduced register \"ledout:inst3\|b\[24\]\" with stuck data_in port to stuck value GND" {  } { { "ledout.v" "" { Text "D:/one/ledout.v" 11 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ledout:inst3\|b\[25\] data_in GND " "Warning (14130): Reduced register \"ledout:inst3\|b\[25\]\" with stuck data_in port to stuck value GND" {  } { { "ledout.v" "" { Text "D:/one/ledout.v" 11 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ledout:inst3\|b\[26\] data_in GND " "Warning (14130): Reduced register \"ledout:inst3\|b\[26\]\" with stuck data_in port to stuck value GND" {  } { { "ledout.v" "" { Text "D:/one/ledout.v" 11 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ledout:inst3\|b\[27\] data_in GND " "Warning (14130): Reduced register \"ledout:inst3\|b\[27\]\" with stuck data_in port to stuck value GND" {  } { { "ledout.v" "" { Text "D:/one/ledout.v" 11 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "fp50HZ:inst11\|Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"fp50HZ:inst11\|Add0\"" {  } { { "fp50HZ.v" "Add0" { Text "D:/one/fp50HZ.v" 12 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "fp50000000HZ:inst10\|Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"fp50000000HZ:inst10\|Add0\"" {  } { { "fp50000000HZ.v" "Add0" { Text "D:/one/fp50000000HZ.v" 12 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "fp50HZ:inst11\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"fp50HZ:inst11\|lpm_add_sub:Add0\"" {  } { { "fp50HZ.v" "" { Text "D:/one/fp50HZ.v" 12 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/addcore.tdf" 76 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "fp50HZ:inst11\|lpm_add_sub:Add0\|addcore:adder fp50HZ:inst11\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"fp50HZ:inst11\|lpm_add_sub:Add0\|addcore:adder\", which is child of megafunction instantiation \"fp50HZ:inst11\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } { "fp50HZ.v" "" { Text "D:/one/fp50HZ.v" 12 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "fp50HZ:inst11\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"fp50HZ:inst11\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Info: Parameter \"LPM_WIDTH\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "fp50HZ.v" "" { Text "D:/one/fp50HZ.v" 12 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "fp50HZ:inst11\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node fp50HZ:inst11\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"fp50HZ:inst11\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"fp50HZ:inst11\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/addcore.tdf" 97 2 0 } } { "fp50HZ.v" "" { Text "D:/one/fp50HZ.v" 12 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "fp50HZ:inst11\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"fp50HZ:inst11\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Info: Parameter \"LPM_WIDTH\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "fp50HZ.v" "" { Text "D:/one/fp50HZ.v" 12 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "fp50HZ:inst11\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node fp50HZ:inst11\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"fp50HZ:inst11\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"fp50HZ:inst11\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/addcore.tdf" 123 6 0 } } { "fp50HZ.v" "" { Text "D:/one/fp50HZ.v" 12 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}