prev_cmp_one.map.qmsg

verilog设计的4位频率计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 17 09:52:03 2008 " "Info: Processing started: Thu Jul 17 09:52:03 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off one -c one " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off one -c one" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "count10.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file count10.v" { { "Info" "ISGN_ENTITY_NAME" "1 count10 " "Info: Found entity 1: count10" {  } { { "count10.v" "" { Text "D:/one/count10.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "gz2 packed ctr.v(3) " "Warning (10227): Verilog HDL Port Declaration warning at ctr.v(3): data type declaration for \"gz2\" declares packed dimensions but the port declaration declaration does not" {  } { { "ctr.v" "" { Text "D:/one/ctr.v" 3 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "gz2 ctr.v(6) " "Info (10151): Verilog HDL Declaration information at ctr.v(6): \"gz2\" is declared here" {  } { { "ctr.v" "" { Text "D:/one/ctr.v" 6 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "ctr.v(7) " "Warning (10268): Verilog HDL information at ctr.v(7): Always Construct contains both blocking and non-blocking assignments" {  } { { "ctr.v" "" { Text "D:/one/ctr.v" 7 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ctr.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ctr.v" { { "Info" "ISGN_ENTITY_NAME" "1 ctr " "Info: Found entity 1: ctr" {  } { { "ctr.v" "" { Text "D:/one/ctr.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fp100HZ.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fp100HZ.v" { { "Info" "ISGN_ENTITY_NAME" "1 fp100HZ " "Info: Found entity 1: fp100HZ" {  } { { "fp100HZ.v" "" { Text "D:/one/fp100HZ.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fp50HZ.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fp50HZ.v" { { "Info" "ISGN_ENTITY_NAME" "1 fp50HZ " "Info: Found entity 1: fp50HZ" {  } { { "fp50HZ.v" "" { Text "D:/one/fp50HZ.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "latch_16.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file latch_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 latch_16 " "Info: Found entity 1: latch_16" {  } { { "latch_16.v" "" { Text "D:/one/latch_16.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "ledout.v(11) " "Warning (10268): Verilog HDL information at ledout.v(11): Always Construct contains both blocking and non-blocking assignments" {  } { { "ledout.v" "" { Text "D:/one/ledout.v" 11 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ledout.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ledout.v" { { "Info" "ISGN_ENTITY_NAME" "1 ledout " "Info: Found entity 1: ledout" {  } { { "ledout.v" "" { Text "D:/one/ledout.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "one.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file one.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 one " "Info: Found entity 1: one" {  } { { "one.bdf" "" { Schematic "D:/one/one.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "latch_8.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file latch_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 latch_8 " "Info: Found entity 1: latch_8" {  } { { "latch_8.v" "" { Text "D:/one/latch_8.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fp4HZ.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fp4HZ.v" { { "Info" "ISGN_ENTITY_NAME" "1 fp4HZ " "Info: Found entity 1: fp4HZ" {  } { { "fp4HZ.v" "" { Text "D:/one/fp4HZ.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fp50000000HZ.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fp50000000HZ.v" { { "Info" "ISGN_ENTITY_NAME" "1 fp50000000HZ " "Info: Found entity 1: fp50000000HZ" {  } { { "fp50000000HZ.v" "" { Text "D:/one/fp50000000HZ.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "one " "Info: Elaborating entity \"one\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ledout ledout:inst3 " "Info: Elaborating entity \"ledout\" for hierarchy \"ledout:inst3\"" {  } { { "one.bdf" "inst3" { Schematic "D:/one/one.bdf" { { 736 1064 1216 864 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fp50HZ fp50HZ:inst11 " "Info: Elaborating entity \"fp50HZ\" for hierarchy \"fp50HZ:inst11\"" {  } { { "one.bdf" "inst11" { Schematic "D:/one/one.bdf" { { 56 408 504 152 "inst11" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 fp50HZ.v(12) " "Warning (10230): Verilog HDL assignment warning at fp50HZ.v(12): truncated value with size 32 to match size of target (8)" {  } { { "fp50HZ.v" "" { Text "D:/one/fp50HZ.v" 12 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}