ledout.v

verilog设计的4位频率计

module ledout(a,clk,clr,k,led_out,led_b);//clk:1HZ
input clk,clr;
input [27:0]a;
input [1:0]k;
output [7:0]led_out,led_b;
reg [7:0] led_out,led_b;
reg [27:0] b;
reg[2:0] i;
reg[3:0] disp_dat;

always @(posedge clk)
 begin
  case(k)
  2'b00://5wei
   begin
    b[3:0]<=a[3:0];
    b[7:4]<=a[7:4];
    b[11:8]<=a[11:8];
    b[15:12]<=a[15:12];
    b[19:16]<=a[19:16];
   end
  2'b01://6wei
   begin
    b[3:0]<=a[7:4];
    b[7:4]<=a[11:8];
    b[11:8]<=4'b1111;
    b[15:12]<=a[15:12];
    b[19:16]<=a[19:16];
    b[23:20]<=a[23:20];
    end
  2'b10://7wei
    begin
    b[3:0]<=a[11:8];
    b[7:4]<=a[15:12];
    b[11:8]<=a[19:16];
    b[15:12]<=a[23:20];
    b[19:16]<=4'b1111;
    b[23:20]<=a[27:24];
    end
   default:b[27:0]<=0;
  endcase
  if(clr)i<=0;
  else 
   begin
    i<=i+1'b1;
   end



 case(i)  //duan      
 3'b000: disp_dat =b[3:0];  
 3'b001: disp_dat =b[7:4]; 
 3'b010: disp_dat =b[11:8]; 
 3'b011: disp_dat =b[15:12]; 
 3'b100: disp_dat =b[19:16]; 
 3'b101: disp_dat =b[23:20]; 
 3'b110: disp_dat =b[27:24]; 
 default:disp_dat=4'b1110;
 endcase 
 
 case(i)//wei
 3'b000:led_b<=8'b10000000;
 3'b001:led_b<=8'b01000000;
 3'b010:led_b<=8'b00100000;
 3'b011:led_b<=8'b00010000;
 3'b100:led_b<=8'b00001000;
 3'b101:led_b<=8'b00000100;
 3'b110:led_b<=8'b00000010;
 3'b111:led_b<=8'b00000001;
 endcase
 end

always@(disp_dat)
 begin
  case(disp_dat)
4'b0000:led_out=8'hc0;
4'b0001:led_out=8'hf9;
4'b0010:led_out=8'ha4;
4'b0011:led_out=8'hb0;
4'b0100:led_out=8'h99;
4'b0101:led_out=8'h92;
4'b0110:led_out=8'h82;
4'b0111:led_out=8'hf8;
4'b1000:led_out=8'h80;
4'b1001:led_out=8'h90;
4'b1111:led_out=8'b01111111;
 default:led_out=8'b11111111;
  endcase
  end
 
endmodule