one.tan.rpt

verilog设计的4位频率计

+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EPF10K10LC84-4     ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk_50M         ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; clk2            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk_50M'                                                                                                                                                                                                                                                  ;
+-----------------------------------------+-----------------------------------------------------+------------------------------+------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                         ; To                           ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------+------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 15.20 MHz ( period = 65.800 ns )                    ; count10:inst9|out[1]         ; latch_16:inst2|qo[25]        ; clk_50M    ; clk_50M  ; None                        ; None                      ; 3.400 ns                ;
; N/A                                     ; 15.27 MHz ( period = 65.500 ns )                    ; count10:inst9|out[2]         ; latch_16:inst2|qo[26]        ; clk_50M    ; clk_50M  ; None                        ; None                      ; 3.400 ns                ;
; N/A                                     ; 15.60 MHz ( period = 64.100 ns )                    ; count10:inst9|out[3]         ; latch_16:inst2|qo[27]        ; clk_50M    ; clk_50M  ; None                        ; None                      ; 1.800 ns                ;
; N/A                                     ; 15.60 MHz ( period = 64.100 ns )                    ; count10:inst9|out[0]         ; latch_16:inst2|qo[24]        ; clk_50M    ; clk_50M  ; None                        ; None                      ; 1.800 ns                ;
; N/A                                     ; 16.10 MHz ( period = 62.100 ns )                    ; count10:inst9|out[2]         ; count10:inst9|out[1]         ; clk_50M    ; clk_50M  ; None                        ; None                      ; 5.200 ns                ;
; N/A                                     ; 16.10 MHz ( period = 62.100 ns )                    ; count10:inst9|out[1]         ; count10:inst9|out[1]         ; clk_50M    ; clk_50M  ; None                        ; None                      ; 5.200 ns                ;
; N/A                                     ; 16.10 MHz ( period = 62.100 ns )                    ; count10:inst9|out[0]         ; count10:inst9|out[1]         ; clk_50M    ; clk_50M  ; None                        ; None                      ; 5.200 ns                ;
; N/A                                     ; 16.23 MHz ( period = 61.600 ns )                    ; count10:inst9|out[2]         ; count10:inst9|out[3]         ; clk_50M    ; clk_50M  ; None                        ; None                      ; 4.700 ns                ;
; N/A                                     ; 16.23 MHz ( period = 61.600 ns )                    ; count10:inst9|out[1]         ; count10:inst9|out[3]         ; clk_50M    ; clk_50M  ; None                        ; None                      ; 4.700 ns                ;
; N/A                                     ; 16.23 MHz ( period = 61.600 ns )                    ; count10:inst9|out[0]         ; count10:inst9|out[3]         ; clk_50M    ; clk_50M  ; None                        ; None                      ; 4.700 ns                ;
; N/A                                     ; 16.23 MHz ( period = 61.600 ns )                    ; count10:inst9|out[3]         ; count10:inst9|out[1]         ; clk_50M    ; clk_50M  ; None                        ; None                      ; 4.700 ns                ;
; N/A                                     ; 16.37 MHz ( period = 61.100 ns )                    ; count10:inst9|out[3]         ; count10:inst9|out[3]         ; clk_50M    ; clk_50M  ; None                        ; None                      ; 4.200 ns                ;
; N/A                                     ; 16.89 MHz ( period = 59.200 ns )                    ; count10:inst9|out[1]         ; count10:inst9|out[2]         ; clk_50M    ; clk_50M  ; None                        ; None                      ; 2.300 ns                ;
; N/A                                     ; 16.89 MHz ( period = 59.200 ns )                    ; count10:inst9|out[0]         ; count10:inst9|out[2]         ; clk_50M    ; clk_50M  ; None                        ; None                      ; 2.300 ns                ;
; N/A                                     ; 17.04 MHz ( period = 58.700 ns )                    ; count10:inst9|out[2]         ; count10:inst9|out[2]         ; clk_50M    ; clk_50M  ; None                        ; None                      ; 1.800 ns                ;
; N/A                                     ; 17.04 MHz ( period = 58.700 ns )                    ; count10:inst9|out[0]         ; count10:inst9|out[0]         ; clk_50M    ; clk_50M  ; None                        ; None                      ; 1.800 ns                ;
; N/A                                     ; 18.05 MHz ( period = 55.400 ns )                    ; count10:inst8|out[1]         ; latch_16:inst2|qo[21]        ; clk_50M    ; clk_50M  ; None                        ; None                      ; 3.400 ns                ;
; N/A                                     ; 18.18 MHz ( period = 55.000 ns )                    ; count10:inst8|out[2]         ; latch_16:inst2|qo[22]        ; clk_50M    ; clk_50M  ; None                        ; None                      ; 3.300 ns                ;
; N/A                                     ; 18.73 MHz ( period = 53.400 ns )                    ; count10:inst8|out[3]         ; latch_16:inst2|qo[23]        ; clk_50M    ; clk_50M  ; None                        ; None                      ; 1.800 ns                ;
; N/A                                     ; 18.73 MHz ( period = 53.400 ns )                    ; count10:inst8|out[0]         ; latch_16:inst2|qo[20]        ; clk_50M    ; clk_50M  ; None                        ; None                      ; 1.800 ns                ;
; N/A                                     ; 19.31 MHz ( period = 51.800 ns )                    ; count10:inst8|out[2]         ; count10:inst8|out[1]         ; clk_50M    ; clk_50M  ; None                        ; None                      ; 5.200 ns                ;
; N/A                                     ; 19.31 MHz ( period = 51.800 ns )                    ; count10:inst8|out[1]         ; count10:inst8|out[1]         ; clk_50M    ; clk_50M  ; None                        ; None                      ; 5.200 ns                ;
; N/A                                     ; 19.31 MHz ( period = 51.800 ns )                    ; count10:inst8|out[0]         ; count10:inst8|out[1]         ; clk_50M    ; clk_50M  ; None                        ; None                      ; 5.200 ns                ;