ctr.v.bak

verilog设计的4位频率计

 module ctr(clk,rst,k1,k2,k3,count_en,count_clr,load,gz2);
output count_en,count_clr,load;
output  gz2;
input clk,rst,k1,k2,k3;
reg count_en,load,kk;
reg [1:0]gz2;
always @(posedge clk)
 begin
 case({k1,k2,k3})
   3'b100:gz2<=2'b00;//5
   3'b010:gz2<=2'b01;//6
   3'b001:gz2<=2'b10;//7
   default:gz2<=2'b11;
  endcase


  if(rst)
    begin
     count_en<=0;
     load<=1;
    end
  else
     begin
      count_en<=~count_en;
      load<=count_en;//load:xinhao
     end
 end
 assign count_clr=~clk&load;
endmodule