stopwatch.ucf

verilog HDL语言编写的数字秒表

NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 18.5 ns HIGH 50 % INPUT_JITTER 0.06 ns;
INST "seg_a" TNM = "display_grp";
INST "seg_b" TNM = "display_grp";
INST "seg_c" TNM = "display_grp";
INST "seg_d" TNM = "display_grp";
INST "seg_dp" TNM = "display_grp";
INST "seg_e" TNM = "display_grp";
INST "seg_f" TNM = "display_grp";
INST "seg_g" TNM = "display_grp";
TIMEGRP "display_grp" OFFSET = OUT 11.5 ns AFTER "clk"  ;
#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "an<0>"  LOC = "d14"  ;
NET "an<1>"  LOC = "g14"  ;
NET "an<2>"  LOC = "f14"  ;
NET "an<3>"  LOC = "e13"  ;
NET "clk"  LOC = "T9"  ; 
NET "reset"  LOC = "L13"  ; 
NET "seg_a"  LOC = "E14"  ; 
NET "seg_b"  LOC = "G13"  ; 
NET "seg_c"  LOC = "N15"  ; 
NET "seg_d"  LOC = "P15"  ; 
NET "seg_dp"  LOC = "P16"  ;
NET "seg_e"  LOC = "R16"  ;
NET "seg_f"  LOC = "F13"  ;
NET "seg_g"  LOC = "N16"  ;
NET "strtstop"  LOC = "M13"  ; 

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE