16count2.v.bak

来自「用VERILOG实现的秒表 用VERILOG实现的秒表」· BAK 代码 · 共 24 行

module 16count(clk,reset,out1,out2,out3,out4);
  input clk,reset;
  output [3:0] out1,out2,out3,out4;
  wire [3:0] out1,out2,out3,out4;
  reg [15:0] count;

  always@(posedge clk or posedge reset)
     begin
       if (reset==1'b1)
         count[15:0]<=16'h0000;
       else if (count[3:0]<9)
            count<=count+1;
       else if (count[3:0]==4'b1001)
            count<=count+7;
       else if (count[7:0]==8'b10011001)
            count<=count+49;
       else if (count[11:0]==12'b100110011001)
            count<=count+343;
     end
  assign out1=count[3:0];
  assign out2=count{7:4];
  assign out3=count[11:8];
  assign out4=count[15:12];
 endmodule