secondwatch.tan.summary

用VERILOG实现的秒表 用VERILOG实现的秒表

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : -2.318 ns
From           : reset_n
To             : fpcount:fpcount_sl|cp
From Clock     : --
To Clock       : clkin
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 22.579 ns
From           : jscount:jscount_sl|count[0]
To             : seven[3]
From Clock     : clkin
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 5.636 ns
From           : reset_n
To             : fpcount:fpcount_sl|cp
From Clock     : --
To Clock       : clkin
Failed Paths   : 0

Type           : Clock Setup: 'clkin'
Slack          : N/A
Required Time  : None
Actual Time    : 128.27 MHz ( period = 7.796 ns )
From           : fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|safe_q[15]
To             : fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|safe_q[15]
From Clock     : clkin
To Clock       : clkin
Failed Paths   : 0

Type           : Clock Hold: 'clkin'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : jscount:jscount_sl|count[3]
To             : jscount:jscount_sl|count[3]
From Clock     : clkin
To Clock       : clkin
Failed Paths   : 53

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 53

--------------------------------------------------------------------------------------