16count.v

来自「用VERILOG实现的秒表 用VERILOG实现的秒表」· Verilog 代码 · 共 65 行

module sixteencount(reset,clk,out1,out2,out3,out4);
  
  input clk,reset;
  output [3:0] out1,out2,out3,out4;
  reg [3:0] out1,out2,out3,out4;
  reg cn1,cn2,cn3;

  always@(posedge clk or posedge reset)
    begin
     if (reset==1'b1)
       begin
        {out1,out2,out3,out4}<=16'h0000;
         cn1<=0;
         cn2<=0;
         cn3<=0;
       end
     else if(out1<10)
       begin
        out1<=out1+1;
        cn1<=0;
       end
     else if(out1==4'b1010)
       begin
         out1<=4'h0;
	     cn1<=1;
       end
     else out1=4'h0;
    end

  always@(posedge cn1)
    begin
      if (out2 < 10)
        begin
	      out2<=out2+1;
	      cn2<=0;
	    end
      else  if (out2==4'b1010)
        begin
	     out2<=4'h0;
	     cn2<=1;
	    end
     end

 always@(posedge cn2)
   begin
     if (out3 < 10)
	     begin
	     out3<=out3+1;
	     cn3<=0;
	     end
      else if (out3==4'b1010)
	     begin
	     out3<=4'h0;
	     cn3<=1;
	     end
    end

  always@(posedge cn3)
   begin
     if (out4 < 10)
	  out4<=out4+1;
      else if (out4==4'b1010)
	  out4<=4'h0;
    end
endmodule