8count.v

来自「用VERILOG实现的秒表 用VERILOG实现的秒表」· Verilog 代码 · 共 29 行

module fpcount(clk,reset,clk_fp);
  
  parameter width=8;
  input clk;
  input reset;
  output clk_fp;
  reg cp;
  reg[width-1:0] cout;

assign clk_fp=cp;
  
 always@(posedge clk or posedge reset)
  begin 
   if(reset==1'b1)
     cout<=8'h00;
   else if(cout<128)
     begin
       cout<=cout+1;
       cp<=1;
     end
   else if(cout>127)
     begin
       cout<=cout+1;
       cp<=0;
     end
   else if(cout==8'hff)
     cout<=8'h00;
   end
endmodule