dpll_2kcount_tp.v

这是基于verilog语言写的

module DPLL_2KCOUNT_tp;
reg[3:0] k;
reg se,reset,kclock;
wire carry,borrow;

parameter dely=100;
DPLL_2KCOUNT inst_DPLL_2KCOUNT(se,reset,k,kclock,carry,borrow);

initial
begin se=0;reset=0;k=5;kclock=0;
# (dely*20)  reset=1;
# (dely*20)  se=1;
# (dely*20)  k=3;
# (dely*20)  k=6;
#(dely*20)   se=0;
# (dely*20)  k=12;
# (dely*50)  $stop;
end

always# (dely/2) kclock=~kclock;

initial
$monitor($time,,,"se=%d reset=%d k=%d kclock=%d carry=%d borrow=%d ",se,reset,k,kclock,carry,borrow);
endmodule