dpll_two.v

来自「这是基于verilog语言写的」· Verilog 代码 · 共 25 行

module DPLL_two(fout2,fout,reset);
output fout;
input  fout2,reset;
reg fout;
reg[7:0] out4;

always @(posedge fout2 or negedge reset )
  begin
     if (reset==0) 
        begin
            out4<=0;fout<=0;
        end
     else if(reset==1)
        begin  
           if(out4==1)
              begin
                out4<=0;fout<=1;
              end
           else if(out4!=1) 
              begin
                out4<=out4+1;fout<=0;
              end
        end
  end
endmodule