dpll_xor_tp.v.bak

这是基于verilog语言写的

module DPLL_xor_tp;
reg fin,fout;
wire se;

parameter dely=100;
DPLL_xor inst_DPLL_xor(fin,fout,se);

initial
begin fin=0;fout=0;
#(dely*10)  fout=1;
#(dely*10)  $stop;
end

always#(dely/2) fin=~fin;

initial
$monitor($time,,,"fin=%d fout=%d se=%d",fin,fout,se);
endmodule