dpll_2kcount.v.bak

这是基于verilog语言写的

module DPLL_2KCOUNT(se,reset,k,kclock,carry,borrow);
output carry,borrow;
input[3:0] k;
input  se,reset,kclock;
reg[19:0] out;
reg[19:0] mo;
always @(k)
  begin
      case(k)
      4'b0001:mo<=7;
      4'b0010:mo<=15;
      4'b0011:mo<=31;
      4'b0100:mo<=63;
      4'b0101:mo<=127;
      4'b0110:mo<=255;
      4'b0111:mo<=511;
      4'b1000:mo<=1023;
      4'b1001:mo<=2047;
      4'b1010:mo<=4095;
      4'b1011:mo<=8191;
      4'b1100:mo<=16383;
      4'd1101:mo<=32767;
      4'd1110:mo<=65535;
      4'd1111:mo<=131072;
       default:mo<=7;
      endcase 
   end
     
always @(posedge kclock or posedge reset)
   begin
     if(reset==0) out<=0;
     else if(reset==1)
        begin
           if(se==1) 
              begin
                 if(out!=0)   out<=out-1;
                 else if(out==0)  out<=mo; 
              end
           else if(se==0)
              begin
                 if(out!=mo) out<=out+1; 
                 else if(out==mo)   out<=0;
              end
        end  
   end
assign carry=(!reset)&(!se)&(out==mo);
assign borrow=(!reset)&se&(out==0);
endmodule