ffd.txt

这是基于verilog语言写的

module FFD(idclock,reset,a,b,c);
input idclock,reset,a;
output b,c;
reg b,c;

always@(posedge idclock or posedge reset);
begin
   if(!reset) b<=0;c<=1;
   else if(reset) begin b<=(~a);c<=a;end
end

endmodule