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📄 dac0832.rpt

📁 用Verilog HDL编写的0832源程序
💻 RPT
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-- Node name is ':31' = 'count8' 
-- Equation name is 'count8', location is LC3_D18, type is buried.
count8   = DFFE( _EQ008, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ008 = !count7 &  count8
         # !count6 &  count8
         #  count8 & !_LC2_D2
         #  count6 &  count7 & !count8 &  _LC2_D2;

-- Node name is ':30' = 'count9' 
-- Equation name is 'count9', location is LC1_D12, type is buried.
count9   = DFFE( _EQ009, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ009 =  count9 & !_LC2_D18
         # !count9 &  _LC2_D18;

-- Node name is ':29' = 'count10' 
-- Equation name is 'count10', location is LC4_D12, type is buried.
count10  = DFFE( _EQ010, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ010 = !count9 &  count10
         #  count10 & !_LC2_D18
         #  count9 & !count10 &  _LC2_D18;

-- Node name is ':28' = 'count11' 
-- Equation name is 'count11', location is LC2_D12, type is buried.
count11  = DFFE( _EQ011, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ011 = !count10 &  count11
         # !count9 &  count11
         #  count11 & !_LC2_D18
         #  count9 &  count10 & !count11 &  _LC2_D18;

-- Node name is ':27' = 'count12' 
-- Equation name is 'count12', location is LC3_D12, type is buried.
count12  = DFFE( _EQ012, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ012 =  count12 & !_LC5_D12
         # !count12 &  _LC5_D12;

-- Node name is ':26' = 'count13' 
-- Equation name is 'count13', location is LC6_D12, type is buried.
count13  = DFFE( _EQ013, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ013 = !count12 &  count13
         #  count13 & !_LC5_D12
         #  count12 & !count13 &  _LC5_D12;

-- Node name is ':25' = 'count14' 
-- Equation name is 'count14', location is LC8_D12, type is buried.
count14  = DFFE( _EQ014, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ014 = !count13 &  count14
         # !count12 &  count14
         #  count14 & !_LC5_D12
         #  count12 &  count13 & !count14 &  _LC5_D12;

-- Node name is 'dat0' 
-- Equation name is 'dat0', type is output 
dat0     =  _LC1_C8;

-- Node name is 'dat1' 
-- Equation name is 'dat1', type is output 
dat1     =  _LC2_E8;

-- Node name is 'dat2' 
-- Equation name is 'dat2', type is output 
dat2     =  _LC1_E10;

-- Node name is 'dat3' 
-- Equation name is 'dat3', type is output 
dat3     =  _LC5_E9;

-- Node name is 'dat4' 
-- Equation name is 'dat4', type is output 
dat4     =  _LC2_E11;

-- Node name is 'dat5' 
-- Equation name is 'dat5', type is output 
dat5     =  _LC4_C12;

-- Node name is 'dat6' 
-- Equation name is 'dat6', type is output 
dat6     =  _LC4_C16;

-- Node name is 'dat7' 
-- Equation name is 'dat7', type is output 
dat7     =  _LC5_C15;

-- Node name is '|lpm_add_sub:56|addcore:adder|:103' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_D2', type is buried 
_LC6_D2  = LCELL( _EQ015);
  _EQ015 =  count0 &  count1 &  count2;

-- Node name is '|lpm_add_sub:56|addcore:adder|:115' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_D2', type is buried 
_LC2_D2  = LCELL( _EQ016);
  _EQ016 =  count3 &  count4 &  count5 &  _LC6_D2;

-- Node name is '|lpm_add_sub:56|addcore:adder|:127' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_D18', type is buried 
_LC2_D18 = LCELL( _EQ017);
  _EQ017 =  count6 &  count7 &  count8 &  _LC2_D2;

-- Node name is '|lpm_add_sub:56|addcore:adder|:139' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_D12', type is buried 
_LC5_D12 = LCELL( _EQ018);
  _EQ018 =  count9 &  count10 &  count11 &  _LC2_D18;

-- Node name is ':48' 
-- Equation name is '_LC5_C15', type is buried 
_LC5_C15 = DFFE( _EC10_C, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':49' 
-- Equation name is '_LC4_C16', type is buried 
_LC4_C16 = DFFE( _EC2_C, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':50' 
-- Equation name is '_LC4_C12', type is buried 
_LC4_C12 = DFFE( _EC9_C, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':51' 
-- Equation name is '_LC2_E11', type is buried 
_LC2_E11 = DFFE( _EC10_E, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':52' 
-- Equation name is '_LC5_E9', type is buried 
_LC5_E9  = DFFE( _EC2_E, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':53' 
-- Equation name is '_LC1_E10', type is buried 
_LC1_E10 = DFFE( _EC9_E, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':54' 
-- Equation name is '_LC2_E8', type is buried 
_LC2_E8  = DFFE( _EC1_E, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':55' 
-- Equation name is '_LC1_C8', type is buried 
_LC1_C8  = DFFE( _EC1_C, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|romdac:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_0' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC1_C', type is memory 
_EC1_C   = MEMORY_SEGMENT( VCC, GLOBAL( clk), VCC, GND, VCC, count5, count6, count7, count8, count9, count10, count11, count12, count13, count14, VCC, count5, count6, count7, count8, count9, count10, count11, count12, count13, count14, VCC, VCC, VCC, VCC);

-- Node name is '|romdac:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_1' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC1_E', type is memory 
_EC1_E   = MEMORY_SEGMENT( VCC, GLOBAL( clk), VCC, GND, VCC, count5, count6, count7, count8, count9, count10, count11, count12, count13, count14, VCC, count5, count6, count7, count8, count9, count10, count11, count12, count13, count14, VCC, VCC, VCC, VCC);

-- Node name is '|romdac:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_2' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC9_E', type is memory 
_EC9_E   = MEMORY_SEGMENT( VCC, GLOBAL( clk), VCC, GND, VCC, count5, count6, count7, count8, count9, count10, count11, count12, count13, count14, VCC, count5, count6, count7, count8, count9, count10, count11, count12, count13, count14, VCC, VCC, VCC, VCC);

-- Node name is '|romdac:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_3' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC2_E', type is memory 
_EC2_E   = MEMORY_SEGMENT( VCC, GLOBAL( clk), VCC, GND, VCC, count5, count6, count7, count8, count9, count10, count11, count12, count13, count14, VCC, count5, count6, count7, count8, count9, count10, count11, count12, count13, count14, VCC, VCC, VCC, VCC);

-- Node name is '|romdac:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_4' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC10_E', type is memory 
_EC10_E  = MEMORY_SEGMENT( VCC, GLOBAL( clk), VCC, GND, VCC, count5, count6, count7, count8, count9, count10, count11, count12, count13, count14, VCC, count5, count6, count7, count8, count9, count10, count11, count12, count13, count14, VCC, VCC, VCC, VCC);

-- Node name is '|romdac:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_5' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC9_C', type is memory 
_EC9_C   = MEMORY_SEGMENT( VCC, GLOBAL( clk), VCC, GND, VCC, count5, count6, count7, count8, count9, count10, count11, count12, count13, count14, VCC, count5, count6, count7, count8, count9, count10, count11, count12, count13, count14, VCC, VCC, VCC, VCC);

-- Node name is '|romdac:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_6' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC2_C', type is memory 
_EC2_C   = MEMORY_SEGMENT( VCC, GLOBAL( clk), VCC, GND, VCC, count5, count6, count7, count8, count9, count10, count11, count12, count13, count14, VCC, count5, count6, count7, count8, count9, count10, count11, count12, count13, count14, VCC, VCC, VCC, VCC);

-- Node name is '|romdac:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_7' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC10_C', type is memory 
_EC10_C  = MEMORY_SEGMENT( VCC, GLOBAL( clk), VCC, GND, VCC, count5, count6, count7, count8, count9, count10, count11, count12, count13, count14, VCC, count5, count6, count7, count8, count9, count10, count11, count12, count13, count14, VCC, VCC, VCC, VCC);



Project Information                                     g:\dac0832\dac0832.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:07


Memory Allocated
-----------------

Peak memory allocated during compilation  = 23,720K

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