dac0832.v

来自「用Verilog HDL编写的0832源程序」· Verilog 代码 · 共 24 行

module dac0832(
	clk	,
	dat	);

input	clk		;
output	[7:0]dat	;
reg	[14:0]count	;
reg	[7:0]dat	;
reg	[7:0]datt	;

always @(posedge clk)
	count=count+1	;
always @(posedge clk)
	dat=datt	;

romdac
	U1(
	.address(count[14:5])	,
	.inclock(clk)	,
	.q(datt)		);

endmodule