📄 dac0832.rpt
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Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/1728 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4/4
D: 0 8 0 0 0 0 0 0 0 0 0 7 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19/0
E: 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4/4
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 8 0 0 0 0 0 2 1 1 1 8 0 0 1 1 0 4 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27/8
Device-Specific Information: g:\dac0832\dac0832.rpt
dac0832
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G ^ 0 0 0 0 clk
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: g:\dac0832\dac0832.rpt
dac0832
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
68 - - - 07 OUTPUT 0 1 0 0 dat0
67 - - - 08 OUTPUT 0 1 0 0 dat1
65 - - - 09 OUTPUT 0 1 0 0 dat2
64 - - - 10 OUTPUT 0 1 0 0 dat3
63 - - - 11 OUTPUT 0 1 0 0 dat4
62 - - - 12 OUTPUT 0 1 0 0 dat5
60 - - - 15 OUTPUT 0 1 0 0 dat6
59 - - - 16 OUTPUT 0 1 0 0 dat7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: g:\dac0832\dac0832.rpt
dac0832
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - D 02 AND2 0 3 0 4 |lpm_add_sub:56|addcore:adder|:103
- 2 - D 02 AND2 0 4 0 4 |lpm_add_sub:56|addcore:adder|:115
- 2 - D 18 AND2 0 4 0 4 |lpm_add_sub:56|addcore:adder|:127
- 5 - D 12 AND2 0 4 0 3 |lpm_add_sub:56|addcore:adder|:139
- - 1 C -- MEM_SGMT 0 10 0 1 |romdac:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_0
- - 1 E -- MEM_SGMT 0 10 0 1 |romdac:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_1
- - 9 E -- MEM_SGMT 0 10 0 1 |romdac:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_2
- - 2 E -- MEM_SGMT 0 10 0 1 |romdac:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_3
- - 10 E -- MEM_SGMT 0 10 0 1 |romdac:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_4
- - 9 C -- MEM_SGMT 0 10 0 1 |romdac:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_5
- - 2 C -- MEM_SGMT 0 10 0 1 |romdac:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_6
- - 10 C -- MEM_SGMT 0 10 0 1 |romdac:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_7
- 8 - D 12 DFFE + 0 3 0 8 count14 (:25)
- 6 - D 12 DFFE + 0 2 0 9 count13 (:26)
- 3 - D 12 DFFE + 0 1 0 10 count12 (:27)
- 2 - D 12 DFFE + 0 3 0 9 count11 (:28)
- 4 - D 12 DFFE + 0 2 0 10 count10 (:29)
- 1 - D 12 DFFE + 0 1 0 11 count9 (:30)
- 3 - D 18 DFFE + 0 3 0 9 count8 (:31)
- 1 - D 18 DFFE + 0 2 0 10 count7 (:32)
- 4 - D 18 DFFE + 0 1 0 11 count6 (:33)
- 4 - D 02 DFFE + 0 3 0 9 count5 (:34)
- 8 - D 02 DFFE + 0 2 0 2 count4 (:35)
- 7 - D 02 DFFE + 0 1 0 3 count3 (:36)
- 5 - D 02 DFFE + 0 2 0 1 count2 (:37)
- 1 - D 02 DFFE + 0 1 0 2 count1 (:38)
- 3 - D 02 DFFE + 0 0 0 3 count0 (:39)
- 5 - C 15 DFFE + 0 1 1 0 :48
- 4 - C 16 DFFE + 0 1 1 0 :49
- 4 - C 12 DFFE + 0 1 1 0 :50
- 2 - E 11 DFFE + 0 1 1 0 :51
- 5 - E 09 DFFE + 0 1 1 0 :52
- 1 - E 10 DFFE + 0 1 1 0 :53
- 2 - E 08 DFFE + 0 1 1 0 :54
- 1 - C 08 DFFE + 0 1 1 0 :55
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: g:\dac0832\dac0832.rpt
dac0832
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 14/144( 9%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 2/144( 1%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 14/144( 9%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 6/24( 25%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: g:\dac0832\dac0832.rpt
dac0832
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 31 clk
Device-Specific Information: g:\dac0832\dac0832.rpt
dac0832
** EQUATIONS **
clk : INPUT;
-- Node name is ':39' = 'count0'
-- Equation name is 'count0', location is LC3_D2, type is buried.
count0 = DFFE(!count0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':38' = 'count1'
-- Equation name is 'count1', location is LC1_D2, type is buried.
count1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = count0 & !count1
# !count0 & count1;
-- Node name is ':37' = 'count2'
-- Equation name is 'count2', location is LC5_D2, type is buried.
count2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !count0 & count2
# !count1 & count2
# count0 & count1 & !count2;
-- Node name is ':36' = 'count3'
-- Equation name is 'count3', location is LC7_D2, type is buried.
count3 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = count3 & !_LC6_D2
# !count3 & _LC6_D2;
-- Node name is ':35' = 'count4'
-- Equation name is 'count4', location is LC8_D2, type is buried.
count4 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !count3 & count4
# count4 & !_LC6_D2
# count3 & !count4 & _LC6_D2;
-- Node name is ':34' = 'count5'
-- Equation name is 'count5', location is LC4_D2, type is buried.
count5 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !count3 & count5
# count5 & !_LC6_D2
# !count4 & count5
# count3 & count4 & !count5 & _LC6_D2;
-- Node name is ':33' = 'count6'
-- Equation name is 'count6', location is LC4_D18, type is buried.
count6 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = count6 & !_LC2_D2
# !count6 & _LC2_D2;
-- Node name is ':32' = 'count7'
-- Equation name is 'count7', location is LC1_D18, type is buried.
count7 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !count6 & count7
# count7 & !_LC2_D2
# count6 & !count7 & _LC2_D2;
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