test_multiplier_full_add.v

来自「8*8乘法器及其测试：采用booth编码的乘法器：1． ultipler_qui」· Verilog 代码 · 共 48 行

module test_multiplier_full_add;

  reg a;
  reg b;
  reg cin;
  reg clk;
  
  
  wire s;
  wire cout;


multiplier_full_add     multiplier_full_add_1(
    .a                          (a),
    .b                          (b),
    .cin                        (cin),
    .s                          (s),
    .cout                       (cout)
    );


initial 
 begin 
   clk = 0;
   a = 1;
   b = 0;
   cin = 0; 
 end
 
 
 always 
 #20  clk = ~clk;
 
 
endmodule