test_multiplier_unit.v

来自「8*8乘法器及其测试：采用booth编码的乘法器：1． ultipler_qui」· Verilog 代码 · 共 61 行

//-----------------------------------------------------------------
// module: test_multiplier_unit

// file name: multiplier_unit.v

// purpose: test full addr   

// author Hejun 

// simulate Modelsim

//------------------------------------------

// Revision List

// version 1.0


`timescale 	 1ns/1ns

module test_multiplier_unit;

reg [3:0] y;
reg [3:0] x;
reg [1:0] shiftin;
reg cin;
reg clk;
 
wire [3:0] shiftout;
wire [3:0] pp; 
wire cout;
 
 multiplier_unit_4          multiplier_unit_4_1(
    .y                          (y),
    .x                          (x),
    .shiftin                    (shiftin),
    .shiftout                   (shiftout),
  //  .sumin                      (sumin),
  //  .sumout                     (sumout),
    .cin                        (cin),
  //  .cin2                       (cin2),
  //  .cin3                       (cin3),
    .cout                       (cout),
  //  .cout2                      (cout2)
    .pp                         (pp)
    ); 
    

initial
begin
   y[3:0] = 4'b1100;
   x[3:0] = 4'b0110;
   shiftin[1:0] = 2'b10;
   cin = 0;   
   clk = 0;
end    

always
  #20 clk = ~clk;

endmodule