test_multiplier_patial_product.v

来自「8*8乘法器及其测试：采用booth编码的乘法器：1． ultipler_qui」· Verilog 代码 · 共 52 行

//------------------------------------------------------------

// file name : test_multiplier_patial_product 

// module name : test_multiplier_patial_product.v

// author : hejun

//software : model sim

//version : 1.0

//-----------------------------------------------------------


`timescale 	 1ns/1ns


module test_multiplier_patial_product;


reg [7:0] x;
reg [7:0] y;
reg clk;

wire [15:0] pp1;
wire [15:0] pp2;
wire [15:0] pp3;
 
 
 multiplier_patial_product     multiplier_patial_product_1(
      .x                             (x),          
      .y                             (y),
      .pp1                           (pp1),
      .pp2                           (pp2),
      .pp3                           (pp3)
      );
      
      
initial 
  begin 
     x[7:0] = 8'b10110011;
     y[7:0] = 8'b01100101;
     clk = 0;
  end
  
  
always 
   # 20 clk = ~clk;     


endmodule