test_multiplier_top.v

来自「8*8乘法器及其测试：采用booth编码的乘法器：1． ultipler_qui」· Verilog 代码 · 共 51 行

//-------------------------------------------------------

// file test_multiplier_top

// module test_multiplier_top

// author : hejun

// software : model sim

// version : 1.0

//-------------------------------------------------------

`timescale 	 1ns/1ns



module test_multiplier_top;


reg [7:0] ain;
reg [7:0] bin;
reg clk;

wire [15:0] sout;



multiplier_top       multiplier_top_1(
    .x                  (ain),
    .y                  (bin),
    .z                  (sout)
    );



initial  
    begin
       clk = 0;
       ain[7:0] = 8'b00101011;
       bin[7:0] = 8'b00101011;
    end

always
#16  clk = ~clk;


endmodule