multiplier_quick_add_4.v

来自「8*8乘法器及其测试：采用booth编码的乘法器：1． ultipler_qui」· Verilog 代码 · 共 85 行

//----------------------------------------------

// file name: multiplier_quick_add_4

// module: multiplier_quick_add_4.v

// purpose: quick add for 4 bit

// author: hejun
 
// simulate: model sim

//------------------------------------------------

// version 1.0



module multiplier_quick_add_4(
  a,
  b,
  c
  );

input [4:1] a;
input [4:1] b
output [4:1] s;
output cout;

wire [4:1] s;
wire cout;

wire [4:1]c;
wire [4:1] g;
wire [4:1] p;

assign g[4:1] = a[4:1] & b[4:1];
assign p[4:1] = a[4:1] ^ b[4:1];

assign c[1] = g[1];
assign c[2] = g[2] | p[2] & g[1];
assign c[3] = g[3] | p[3] & g[2] | p[3] & p[2] & g[1];
assign c[4] = g[4] | p[4] & g[3] | p[4] & p[3] & g[2] | p[4] & p[3] & p[2] & g[1];


assign s[4:1] = c[4:1] ^ a[4:1] ^ b[4:1];
assign cout = c[4];

endmodule 



module multiplier_quick_add_5(
   a,
   b,
   c
   );
   
input [5:1] a;
input [5:1] b;
output [5:1] s;
output cout;

wire [5:1] s;
wire cout;

wire [5:1] c;
wire [5:1] g;
wire [5:1] p;


assign g[5:1] = a[5:1] & b[5:1];
assign p[5:1] = a[5:1] ^ b[5:1];


assign c[1] = g[1];
assign c[2] = g[2] | p[2] & g[1];
assign c[3] = g[3] | p[3] & g[2] | p[3] & p[2] & g[1];
assign c[4] = g[4] | p[4] & g[3] | p[4] & p[3] & g[2] | p[4] & p[3] & p[2] & g[1];
assign c[5] = g[5] | p[5] & g[4] | p[5] & p[4] & g[3] | p[5] & p[4] & p[3] & g[2] | p[5] & p[4] & p[3] & p[2] & g[1];

assign s[5:1] = c[5:1] ^ a[5:1] ^ b[5:1];
assign cout = c[5];

endmodule