main.map.summary

来自「这是一个用verilog语言设计的数字频率及的源代码」· SUMMARY 代码 · 共 9 行

Flow Status : Successful - Mon Jul 17 23:30:02 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : main
Top-level Entity Name : main
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 251
Total pins : 20