main.map.rpt

这是一个用verilog语言设计的数字频率及的源代码

+----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                          ;
+--------------------------------+------------+------+-----------------------------------------+
; Compilation Hierarchy Node     ; Macrocells ; Pins ; Full Hierarchy Name                     ;
+--------------------------------+------------+------+-----------------------------------------+
; |main                          ; 251        ; 20   ; |main                                   ;
;    |counter:inst|              ; 27         ; 0    ; |main|counter:inst                      ;
;       |lpm_counter:Q0_rtl_1|   ; 4          ; 0    ; |main|counter:inst|lpm_counter:Q0_rtl_1 ;
;       |lpm_counter:Q1_rtl_2|   ; 4          ; 0    ; |main|counter:inst|lpm_counter:Q1_rtl_2 ;
;       |lpm_counter:Q2_rtl_3|   ; 4          ; 0    ; |main|counter:inst|lpm_counter:Q2_rtl_3 ;
;       |lpm_counter:Q3_rtl_4|   ; 4          ; 0    ; |main|counter:inst|lpm_counter:Q3_rtl_4 ;
;       |lpm_counter:Q4_rtl_5|   ; 4          ; 0    ; |main|counter:inst|lpm_counter:Q4_rtl_5 ;
;       |lpm_counter:Q5_rtl_0|   ; 4          ; 0    ; |main|counter:inst|lpm_counter:Q5_rtl_0 ;
;    |data_mux:inst8|            ; 8          ; 0    ; |main|data_mux:inst8                    ;
;    |dispdecoder:inst5|         ; 24         ; 0    ; |main|dispdecoder:inst5                 ;
;    |dispselect:inst7|          ; 9          ; 0    ; |main|dispselect:inst7                  ;
;    |fdiv:inst1|                ; 151        ; 0    ; |main|fdiv:inst1                        ;
;       |lpm_counter:cnt1_rtl_6| ; 35         ; 0    ; |main|fdiv:inst1|lpm_counter:cnt1_rtl_6 ;
;       |lpm_counter:cnt2_rtl_7| ; 36         ; 0    ; |main|fdiv:inst1|lpm_counter:cnt2_rtl_7 ;
;       |lpm_counter:cnt3_rtl_9| ; 36         ; 0    ; |main|fdiv:inst1|lpm_counter:cnt3_rtl_9 ;
;       |lpm_counter:cnt4_rtl_8| ; 36         ; 0    ; |main|fdiv:inst1|lpm_counter:cnt4_rtl_8 ;
;    |flip_latch:inst2|          ; 24         ; 0    ; |main|flip_latch:inst2                  ;
;    |gate_control:inst3|        ; 8          ; 0    ; |main|gate_control:inst3                ;
+--------------------------------+------------+------+-----------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.map.eqn.


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                   ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path                                        ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
; main.bdf                         ; yes             ; E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf             ;
; counter.v                        ; yes             ; E:/戴仙金/资料/Verilog书/源代码/cymometer/main/counter.v            ;
; gate_control.v                   ; yes             ; E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v       ;
; fdiv.v                           ; yes             ; E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v               ;
; dispdecoder.v                    ; yes             ; E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v        ;
; data_mux.v                       ; yes             ; E:/戴仙金/资料/Verilog书/源代码/cymometer/main/data_mux.v           ;
; flip_latch.v                     ; yes             ; E:/戴仙金/资料/Verilog书/源代码/cymometer/main/flip_latch.v         ;
; dispselect.v                     ; yes             ; E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispselect.v         ;
; lpm_counter.tdf                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf         ;
; lpm_constant.inc                 ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_constant.inc        ;
; lpm_decode.inc                   ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_decode.inc          ;
; lpm_add_sub.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_add_sub.inc         ;
; cmpconst.inc                     ; yes             ; d:/altera/quartus42/libraries/megafunctions/cmpconst.inc            ;
; lpm_compare.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_compare.inc         ;
; lpm_counter.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_counter.inc         ;
; dffeea.inc                       ; yes             ; d:/altera/quartus42/libraries/megafunctions/dffeea.inc              ;
; alt_synch_counter.inc            ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_synch_counter.inc   ;
; alt_synch_counter_f.inc          ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc            ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.inc   ;
; alt_counter_stratix.inc          ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal42.inc                    ; yes             ; d:/altera/quartus42/libraries/megafunctions/aglobal42.inc           ;
+----------------------------------+-----------------+---------------------------------------------------------------------+


+--------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary      ;
+----------------------+---------------------------+
; Resource             ; Usage                     ;
+----------------------+---------------------------+
; Logic cells          ; 251                       ;
; Total registers      ; 192                       ;
; I/O pins             ; 20                        ;
; Shareable expanders  ; 26                        ;
; Parallel expanders   ; 9                         ;
; Maximum fan-out node ; gate_control:inst3|wire_1 ;
; Maximum fan-out      ; 56                        ;
; Total fan-out        ; 3213                      ;
; Average fan-out      ; 10.82                     ;
+----------------------+---------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Mon Jul 17 23:29:16 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off main -c main
Info: Found 1 design units, including 1 entities, in source file main.bdf
    Info: Found entity 1: main
Info: Using design file counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: counter
Warning: Verilog HDL unsupported feature warning at counter.v(17): Initial Construct is not supported and will be ignored
Info: Using design file gate_control.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: gate_control
Warning: Verilog HDL unsupported feature warning at gate_control.v(30): Initial Construct is not supported and will be ignored
Warning: Verilog HDL Always Construct warning at gate_control.v(34): variable fref may not be assigned a new value in every possible path through the Always Construct.  Variable fref holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at gate_control.v(34): variable dp_s1hz may not be assigned a new value in every possible path through the Always Construct.  Variable dp_s1hz holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at gate_control.v(34): variable dp_s10hz may not be assigned a new value in every possible path through the Always Construct.  Variable dp_s10hz holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at gate_control.v(34): variable dp_s100hz may not be assigned a new value in every possible path through the Always Construct.  Variable dp_s100hz holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Using design file fdiv.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: fdiv
Info: Using design file dispdecoder.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: dispdecoder
Warning: Verilog HDL unsupported feature warning at dispdecoder.v(26): Initial Construct is not supported and will be ignored
Warning: Verilog HDL Always Construct warning at dispdecoder.v(28): variable data_out may not be assigned a new value in every possible path through the Always Construct.  Variable data_out holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Using design file data_mux.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: data_mux
Info: Using design file flip_latch.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: flip_latch
Info: Using design file dispselect.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: dispselect
Info: Inferred 10 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter:inst|Q5[0]~40"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter:inst|Q0[0]~4"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter:inst|Q1[0]~8"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter:inst|Q2[0]~17"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter:inst|Q3[0]~26"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter:inst|Q4[0]~35"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: "fdiv:inst1|cnt1[0]~32"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: "fdiv:inst1|cnt2[0]~32"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: "fdiv:inst1|cnt4[0]~32"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: "fdiv:inst1|cnt3[0]~32"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "Clock" to global clock signal
    Info: Promoted clock signal driven by pin "F_in" to global clock signal
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "Clock" to global clock signal
    Info: Promoted clock signal driven by pin "F_in" to global clock signal
Info: Implemented 297 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 15 output pins
    Info: Implemented 251 macrocells
    Info: Implemented 26 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
    Info: Processing ended: Mon Jul 17 23:30:02 2006
    Info: Elapsed time: 00:00:47