📄 fdwt_all.csf.msg
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{ Info "ITAN_SCC_LOOP" "3 " "Found combinatorial loop of 3 nodes" { { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~43 " "Node sel_level:sel3\|655~43" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1163 " "Node sel_level:sel3\|655~1163" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1172 " "Node sel_level:sel3\|655~1172" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } }
{ Info "ITAN_SCC_LOOP" "3 " "Found combinatorial loop of 3 nodes" { { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~44 " "Node sel_level:sel3\|655~44" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1182 " "Node sel_level:sel3\|655~1182" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1191 " "Node sel_level:sel3\|655~1191" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } }
{ Info "ITAN_SCC_LOOP" "3 " "Found combinatorial loop of 3 nodes" { { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~45 " "Node sel_level:sel3\|655~45" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1201 " "Node sel_level:sel3\|655~1201" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1210 " "Node sel_level:sel3\|655~1210" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } }
{ Info "ITAN_SCC_LOOP" "3 " "Found combinatorial loop of 3 nodes" { { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~46 " "Node sel_level:sel3\|655~46" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1220 " "Node sel_level:sel3\|655~1220" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1229 " "Node sel_level:sel3\|655~1229" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } }
{ Info "ITAN_SCC_LOOP" "3 " "Found combinatorial loop of 3 nodes" { { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~47 " "Node sel_level:sel3\|655~47" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1239 " "Node sel_level:sel3\|655~1239" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1248 " "Node sel_level:sel3\|655~1248" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } }
{ Info "ITAN_SCC_LOOP" "3 " "Found combinatorial loop of 3 nodes" { { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~48 " "Node sel_level:sel3\|655~48" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1258 " "Node sel_level:sel3\|655~1258" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1267 " "Node sel_level:sel3\|655~1267" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } }
{ Info "ITAN_SCC_LOOP" "3 " "Found combinatorial loop of 3 nodes" { { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~49 " "Node sel_level:sel3\|655~49" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1277 " "Node sel_level:sel3\|655~1277" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1286 " "Node sel_level:sel3\|655~1286" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } }
{ Info "ITAN_SCC_LOOP" "3 " "Found combinatorial loop of 3 nodes" { { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~50 " "Node sel_level:sel3\|655~50" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1296 " "Node sel_level:sel3\|655~1296" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1305 " "Node sel_level:sel3\|655~1305" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } }
{ Info "ITAN_SCC_LOOP" "3 " "Found combinatorial loop of 3 nodes" { { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~51 " "Node sel_level:sel3\|655~51" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1315 " "Node sel_level:sel3\|655~1315" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1324 " "Node sel_level:sel3\|655~1324" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } }
{ Info "ITAN_SCC_LOOP" "3 " "Found combinatorial loop of 3 nodes" { { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~52 " "Node sel_level:sel3\|655~52" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1334 " "Node sel_level:sel3\|655~1334" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1343 " "Node sel_level:sel3\|655~1343" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } }
{ Info "ITAN_SCC_LOOP" "3 " "Found combinatorial loop of 3 nodes" { { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~53 " "Node sel_level:sel3\|655~53" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1353 " "Node sel_level:sel3\|655~1353" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1362 " "Node sel_level:sel3\|655~1362" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } }
{ Info "ITAN_SCC_LOOP" "3 " "Found combinatorial loop of 3 nodes" { { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~54 " "Node sel_level:sel3\|655~54" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1372 " "Node sel_level:sel3\|655~1372" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1381 " "Node sel_level:sel3\|655~1381" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } }
{ Info "ITAN_SCC_LOOP" "3 " "Found combinatorial loop of 3 nodes" { { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~55 " "Node sel_level:sel3\|655~55" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1391 " "Node sel_level:sel3\|655~1391" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1400 " "Node sel_level:sel3\|655~1400" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } }
{ Info "ITAN_SCC_LOOP" "3 " "Found combinatorial loop of 3 nodes" { { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~57 " "Node sel_level:sel3\|655~57" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1429 " "Node sel_level:sel3\|655~1429" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1438 " "Node sel_level:sel3\|655~1438" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } }
{ Info "ITAN_SCC_LOOP" "3 " "Found combinatorial loop of 3 nodes" { { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~40 " "Node sel_level:sel3\|655~40" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1106 " "Node sel_level:sel3\|655~1106" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1115 " "Node sel_level:sel3\|655~1115" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } }
{ Info "ITAN_SCC_LOOP" "3 " "Found combinatorial loop of 3 nodes" { { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~41 " "Node sel_level:sel3\|655~41" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1125 " "Node sel_level:sel3\|655~1125" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1134 " "Node sel_level:sel3\|655~1134" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } }
{ Info "ITAN_SCC_LOOP" "3 " "Found combinatorial loop of 3 nodes" { { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~58 " "Node sel_level:sel3\|655~58" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1448 " "Node sel_level:sel3\|655~1448" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1457 " "Node sel_level:sel3\|655~1457" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } }
{ Info "ITAN_SCC_LOOP" "3 " "Found combinatorial loop of 3 nodes" { { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~59 " "Node sel_level:sel3\|655~59" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1467 " "Node sel_level:sel3\|655~1467" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1476 " "Node sel_level:sel3\|655~1476" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } } } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } } }
{ Warning "WTDB_NO_CLOCKS" "" "Found pins functioning as undefined clocks and/or memory enables" { { Info "ITDB_NODE_MAP_TO_CLK" "Clk " "Assuming node Clk is an undefined clock" { } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 34 1 0 } } } } } { } }
{ Info "ITDB_FULL_CLOCK_REG_RESULT" "Clk Internal 21.14 MHz register FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Register_F:P4\|Reg_R\[0\] register FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Register_F:P5\|Reg_R\[6\] 47.296 ns " "Clock Clk has Internal fmax of 21.14 MHz between source register FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Register_F:P4\|Reg_R\[0\] and destination register FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Register_F:P5\|Reg_R\[6\] (period= 47.296 ns)" { { Info "ITDB_FULL_DATA_PATH_RESULT" "+ Longest register register 46.872 ns " "+ Longest register to register delay is 46.872 ns" { { Info "ITDB_NODE_DELAY" "1 IC(0.000 ns) + CELL(0.132 ns) 0.132 ns LC6_5_M4 REG FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Register_F:P4\|Reg_R\[0\] " "1: + IC(0.000 ns) + CELL(0.132 ns) = 0.132 ns; Loc. = LC6_5_M4; REG Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Register_F:P4\|Reg_R\[0\]'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Register_F:P4|Reg_R[0] } "NODE_NAME" } } } { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\Register_F.v" "" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\Register_F.v" 21 1 0 } } } } { Info "ITDB_NODE_DELAY" "2 IC(0.244 ns) + CELL(0.721 ns) 1.097 ns LC2_5_M4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|temp1\[0\] " "2: + IC(0.244 ns) + CELL(0.721 ns) = 1.097 ns; Loc. = LC2_5_M4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|temp1\[0\]'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "0.965 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Register_F:P4|Reg_R[0] FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|temp1[0] } "NODE_NAME" } } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 2 1 0 } } } } { Info "ITDB_NODE_DELAY" "3 IC(1.862 ns) + CELL(0.730 ns) 3.689 ns LC4_2_L4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|4~124 " "3: + IC(1.862 ns) + CELL(0.730 ns) = 3.689 ns; Loc. = LC4_2_L4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|4~124'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "2.592 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|temp1[0] FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|4~124 } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" 986 23 0 } } } } { Info "ITDB_NODE_DELAY" "4 IC(0.224 ns) + CELL(0.654 ns) 4.567 ns LC2_2_L4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|4~136 " "4: + IC(0.224 ns) + CELL(0.654 ns) = 4.567 ns; Loc. = LC2_2_L4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|4~136'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "0.878 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|4~124 FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|4~136 } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" 986 23 0 } } } } { Info "ITDB_NODE_DELAY" "5 IC(0.218 ns) + CELL(0.294 ns) 5.079 ns LC10_2_L4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|4~139 " "5: + IC(0.218 ns) + CELL(0.294 ns) = 5.079 ns; Loc. = LC10_2_L4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|4~139'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "0.512 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|4~136 FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|4~139 } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" 986 23 0 } } } } { Info "ITDB_NODE_DELAY" "6 IC(0.898 ns) + CELL(0.654 ns) 6.631 ns LC6_4_L4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|4~151 " "6: + IC(0.898 ns) + CELL(0.654 ns) = 6.631 ns; Loc. = LC6_4_L4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|4~151'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "1.552 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|4~139 FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|4~151 } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" 986 23 0 } } } } { Info "ITDB_NODE_DELAY" "7 IC(0.218 ns) + CELL(0.294 ns) 7.143 ns LC5_4_L4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|4~154 " "7: + IC(0.218 ns) + CELL(0.294 ns) = 7.143 ns; Loc. = LC5_4_L4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|4~154'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "0.512 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|4~151 FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|4~154 } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" 986 23 0 } } } } { Info "ITDB_NODE_DELAY" "8 IC(0.218 ns) + CELL(0.654 ns) 8.015 ns LC8_5_L4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|4~166 " "8: + IC(0.218 ns) + CELL(0.654 ns) = 8.015 ns; Loc. = LC8_5_L4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|4~166'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "0.872 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|4~154 FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|4~166 } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" 986 23 0 } } } } { Info "ITDB_NODE_DELAY" "9 IC(0.224 ns) + CELL(0.294 ns) 8.533 ns LC5_5_L4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|4~169 " "9: + IC(0.224 ns) + CELL(0.294 ns) = 8.533 ns; Loc. = LC5_5_L4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|4~169'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "0.518 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|4~166 FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|4~169 } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" 986 23 0 } } } } { Info "ITDB_NODE_DELAY" "10 IC(0.224 ns) + CELL(0.294 ns) 9.051 ns LC2_5_L4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|4~181 " "10: + IC(0.224 ns) + CELL(0.294 ns) = 9.051 ns; Loc. = LC2_5_L4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|4~181'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "0.518 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|4~169 FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|4~181 } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" 986 23 0 } } } } { Info "ITDB_NODE_DELAY" "11 IC(0.224 ns) + CELL(0.294 ns) 9.569 ns LC7_5_L4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|4~184 " "11: + IC(0.224 ns) + CELL(0.294 ns) = 9.569 ns; Loc. = LC7_5_L4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|4~184'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "0.518 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|4~181 FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|4~184 } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" 986 23 0 } } } } { Info "ITDB_NODE_DELAY" "12 IC(2.807 ns) + CELL(0.294 ns) 12.670 ns LC8_8_W4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|4~196 " "12: + IC(2.807 ns) + CELL(0.294 ns) = 12.670 ns; Loc. = LC8_8_W4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|4~196'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "3.101 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|4~184 FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|4~196 } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" 986 23 0 } } } } { Info "ITDB_NODE_DELAY" "13 IC(0.218 ns) + CELL(0.294 ns) 13.182 ns LC4_8_W4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|2~8 " "13: + IC(0.218 ns) + CELL(0.294 ns) = 13.182 ns; Loc. = LC4_8_W4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|2~8'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "0.512 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|4~196 FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|2~8 } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" 985 26 0 } } } } { Info "ITDB_NODE_DELAY" "14 IC(0.218 ns) + CELL(0.294 ns) 13.694 ns LC9_8_W4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|2~7 " "14: + IC(0.218 ns) + CELL(0.294 ns) = 13.694 ns; Loc. = LC9_8_W4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|2~7'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "0.512 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|2~8 FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|2~7 } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" 985 26 0 } } } } { Info "ITDB_NODE_DELAY" "15 IC(1.018 ns) + CELL(0.294 ns) 15.006 ns LC2_5_W4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|2599~731 " "15: + IC(1.018 ns) + CELL(0.294 ns) = 15.006 ns; Loc. = LC2_5_W4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|2599~731'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "1.312 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|lpm_compare:2510|comptree:comparator|comptree:sub_comptree|cmpchain:gt_cmp_end|2~7 FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|2599~731 } "NODE_NAME" } } } { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\Add.v" "" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\Add.v" 58 1 0 } } } } { Info "ITDB_NODE_DELAY" "16 IC(0.230 ns) + CELL(0.654 ns) 15.890 ns LC1_5_W4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|2599~736 " "16: + IC(0.230 ns) + CELL(0.654 ns) = 15.890 ns; Loc. = LC1_5_W4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|2599~736'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "0.884 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|2599~731 FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|2599~736 } "NODE_NAME" } } } { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\Add.v" "" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\Add.v" 58 1 0 } } } } { Info "ITDB_NODE_DELAY" "17 IC(0.230 ns) + CELL(0.294 ns) 16.414 ns LC8_5_W4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|2599~379 " "17: + IC(0.230 ns) + CELL(0.294 ns) = 16.414 ns; Loc. = LC8_5_W4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r1\|2599~379'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "0.524 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|2599~736 FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|2599~379 } "NODE_NAME" } } } { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\Add.v" "" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\Add.v" 58 1 0 } } } } { Info "ITDB_NODE_DELAY" "18 IC(2.097 ns) + CELL(0.920 ns) 19.431 ns LC2_14_S4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|coff_r:coff_r\|lpm_add_sub:2783\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\] " "18: + IC(2.097 ns) + CELL(0.920 ns) = 19.431 ns; Loc. = LC2_14_S4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|coff_r:coff_r\|lpm_add_sub:2783\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\]'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "3.017 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r1|2599~379 FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|coff_r:coff_r|lpm_add_sub:2783|addcore:adder|a_csnbuffer:result_node|cout[0] } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\a_csnbuffer.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\a_csnbuffer.tdf" 18 2 0 } } } } { Info "ITDB_NODE_DELAY" "19 IC(0.000 ns) + CELL(0.650 ns) 20.081 ns LC3_14_S4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|coff_r:coff_r\|lpm_add_sub:2783\|addcore:adder\|a_csnbuffer:result_node\|sout\[1\] " "19: + IC(0.000 ns) + CELL(0.650 ns) = 20.081 ns; Loc. = LC3_14_S4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|coff_r:coff_r\|lpm_add_sub:2783\|addcore:adder\|a_csnbuffer:result_node\|sout\[1\]'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "0.650 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|coff_r:coff_r|lpm_add_sub:2783|addcore:adder|a_csnbuffer:result_node|cout[0] FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|coff_r:coff_r|lpm_add_sub:2783|addcore:adder|a_csnbuffer:result_node|sout[1] } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\a_csnbuffer.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\a_csnbuffer.tdf" 17 2 0 } } } } { Info "ITDB_NODE_DELAY" "20 IC(0.236 ns) + CELL(0.721 ns) 21.038 ns LC3_13_S4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|coff_r:coff_r\|lpm_add_sub:2782\|addcore:adder\|a_csnbuffer:result_node\|sout\[1\] " "20: + IC(0.236 ns) + CELL(0.721 ns) = 21.038 ns; Loc. = LC3_13_S4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|coff_r:coff_r\|lpm_add_sub:2782\|addcore:adder\|a_csnbuffer:result_node\|sout\[1\]'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "0.957 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|coff_r:coff_r|lpm_add_sub:2783|addcore:adder|a_csnbuffer:result_node|sout[1] FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|coff_r:coff_r|lpm_add_sub:2782|addcore:adder|a_csnbuffer:result_node|sout[1] } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\a_csnbuffer.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\a_csnbuffer.tdf" 17 2 0 } } } } { Info "ITDB_NODE_DELAY" "21 IC(0.985 ns) + CELL(0.920 ns) 22.943 ns LC3_10_S4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|coff_r:coff_r\|lpm_add_sub:2781\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] " "21: + IC(0.985 ns) + CELL(0.920 ns) = 22.943 ns; Loc. = LC3_10_S4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|coff_r:coff_r\|lpm_add_sub:2781\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "1.905 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|coff_r:coff_r|lpm_add_sub:2782|addcore:adder|a_csnbuffer:result_node|sout[1] FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|coff_r:coff_r|lpm_add_sub:2781|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\a_csnbuffer.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\a_csnbuffer.tdf" 18 2 0 } } } } { Info "ITDB_NODE_DELAY" "22 IC(0.000 ns) + CELL(0.650 ns) 23.593 ns LC4_10_S4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|coff_r:coff_r\|lpm_add_sub:2781\|addcore:adder\|a_csnbuffer:result_node\|sout\[2\] " "22: + IC(0.000 ns) + CELL(0.650 ns) = 23.593 ns; Loc. = LC4_10_S4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|coff_r:coff_r\|lpm_add_sub:2781\|addcore:adder\|a_csnbuffer:result_node\|sout\[2\]'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "0.650 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|coff_r:coff_r|lpm_add_sub:2781|addcore:adder|a_csnbuffer:result_node|cout[1] FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|coff_r:coff_r|lpm_add_sub:2781|addcore:adder|a_csnbuffer:result_node|sout[2] } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\a_csnbuffer.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\a_csnbuffer.tdf" 17 2 0 } } } } { Info "ITDB_NODE_DELAY" "23 IC(2.757 ns) + CELL(0.920 ns) 27.270 ns LC4_6_H4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|coff_r:coff_r\|lpm_add_sub:2780\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] " "23: + IC(2.757 ns) + CELL(0.920 ns) = 27.270 ns; Loc. = LC4_6_H4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|coff_r:coff_r\|lpm_add_sub:2780\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "3.677 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|coff_r:coff_r|lpm_add_sub:2781|addcore:adder|a_csnbuffer:result_node|sout[2] FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|coff_r:coff_r|lpm_add_sub:2780|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\a_csnbuffer.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\a_csnbuffer.tdf" 18 2 0 } } } } { Info "ITDB_NODE_DELAY" "24 IC(0.000 ns) + CELL(0.650 ns) 27.920 ns LC5_6_H4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|coff_r:coff_r\|lpm_add_sub:2780\|addcore:adder\|a_csnbuffer:result_node\|sout\[3\] " "24: + IC(0.000 ns) + CELL(0.650 ns) = 27.920 ns; Loc. = LC5_6_H4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|coff_r:coff_r\|lpm_add_sub:2780\|addcore:adder\|a_csnbuffer:result_node\|sout\[3\]'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "0.650 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|coff_r:coff_r|lpm_add_sub:2780|addcore:adder|a_csnbuffer:result_node|cout[2] FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|coff_r:coff_r|lpm_add_sub:2780|addcore:adder|a_csnbuffer:result_node|sout[3] } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\a_csnbuffer.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\a_csnbuffer.tdf" 17 2 0 } } } } { Info "ITDB_NODE_DELAY" "25 IC(0.256 ns) + CELL(0.294 ns) 28.470 ns LC3_5_H4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r2\|lpm_compare:2510\|comptree:comparator\|cmpchain:cmp\[0\]\|comptree:comp\|cmpchain:cmp\[1\]\|6 " "25: + IC(0.256 ns) + CELL(0.294 ns) = 28.470 ns; Loc. = LC3_5_H4; COMB Node = 'FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r2\|lpm_compare:2510\|comptree:comparator\|cmpchain:cmp\[0\]\|comptree:comp\|cmpchain:cmp\[1\]\|6'" { } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" "" "" { Report "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL_everyone_V1_cmp.qrpt" Compiler "FDWT_ALL" "everyone" "V1" "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\db\\FDWT_ALL.quartus_db" { Floorplan "" "" "0.550 ns" { FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|coff_r:coff_r|lpm_add_sub:2780|addcore:adder|a_csnbuffer:result_node|sout[3] FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Add:add_r2|lpm_compare:2510|comptree:comparator|cmpchain:cmp[0]|comptree:comp|cmpchain:cmp[1]|6 } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" 468 44 0 } } } } { Info "ITDB_NODE_DELAY" "26 IC(0.224 ns) + CELL(0.730 ns) 29.424 ns LC7_5_H4 COMB FDWT97_TOP:FDWT\|FDWT97_DataPath:DataPath\|Add:add_r2\|lpm_compare:2510\|comptree:comparator\|comptree:sub_comptree\|cmpchain:gt_cmp_end\|4~136 " "26: + IC(0.224 ns) + CELL(0.730 ns) = 29.424 ns; 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