fdwt_all.csf.msg

来自「這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder」· MSG 代码 · 共 108 行 · 第 1/5 页

 " "Verilog Design File information: Continuing analyzing of source file \"PctoFPGA.v\"
" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v\"
" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"FDWT97_TOP.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"FDWT97_TOP.v\"
" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"FDWT97_TOP.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"FDWT97_TOP.v\"
" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"FDWT97_TOP.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"FDWT97_TOP.v\"
" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v\"
" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"IDWT97_TOP.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"IDWT97_TOP.v\"
" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"IDWT97_TOP.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"IDWT97_TOP.v\"