fdwt_all.csf.msg

這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder

{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\Register_F.v " "Found 1 design units and 1 entities in source file F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\Register_F.v" { { Info "ISGN_ENTITY_NAME" "1 Register_F " "Found entity 1: Register_F" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\Register_F.v" "Register_F" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\Register_F.v" 2 -1 0 } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\Add.v " "Found 1 design units and 1 entities in source file F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\Add.v" { { Info "ISGN_ENTITY_NAME" "1 Add " "Found entity 1: Add" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\Add.v" "Add" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\Add.v" 2 -1 0 } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 C:\\quartus\\libraries\\megafunctions\\lpm_compare.tdf " "Found 1 design units and 1 entities in source file C:\\quartus\\libraries\\megafunctions\\lpm_compare.tdf" { { Info "ISGN_ENTITY_NAME" "1 lpm_compare " "Found entity 1: lpm_compare" {  } { { "C:\\quartus\\libraries\\megafunctions\\lpm_compare.tdf" "lpm_compare" "" { Text "C:\\quartus\\libraries\\megafunctions\\lpm_compare.tdf" 261 1 0 } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 C:\\quartus\\libraries\\megafunctions\\comptree.tdf " "Found 1 design units and 1 entities in source file C:\\quartus\\libraries\\megafunctions\\comptree.tdf" { { Info "ISGN_ENTITY_NAME" "1 comptree " "Found entity 1: comptree" {  } { { "C:\\quartus\\libraries\\megafunctions\\comptree.tdf" "comptree" "" { Text "C:\\quartus\\libraries\\megafunctions\\comptree.tdf" 108 1 0 } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf " "Found 1 design units and 1 entities in source file C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" { { Info "ISGN_ENTITY_NAME" "1 cmpchain " "Found entity 1: cmpchain" {  } { { "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" "cmpchain" "" { Text "C:\\quartus\\libraries\\megafunctions\\cmpchain.tdf" 90 1 0 } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\coff_a.v " "Found 1 design units and 1 entities in source file F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\coff_a.v" { { Info "ISGN_ENTITY_NAME" "1 coff_a " "Found entity 1: coff_a" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\coff_a.v" "coff_a" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\coff_a.v" 1 -1 0 } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\coff_b.v " "Found 1 design units and 1 entities in source file F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\coff_b.v" { { Info "ISGN_ENTITY_NAME" "1 coff_b " "Found entity 1: coff_b" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\coff_b.v" "coff_b" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\coff_b.v" 1 -1 0 } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\coff_r.v " "Found 1 design units and 1 entities in source file F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\coff_r.v" { { Info "ISGN_ENTITY_NAME" "1 coff_r " "Found entity 1: coff_r" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\coff_r.v" "coff_r" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\coff_r.v" 1 -1 0 } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\coff_l.v " "Found 1 design units and 1 entities in source file F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\coff_l.v" { { Info "ISGN_ENTITY_NAME" "1 coff_l " "Found entity 1: coff_l" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\coff_l.v" "coff_l" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\coff_l.v" 1 -1 0 } }  } }  } {  }  }
{  Warning "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "IDWT97_TOP:IDWT\|IDWT97_Control:Control\|CurrentState\[2\] data_in GND " "Reduced register IDWT97_TOP:IDWT\|IDWT97_Control:Control\|CurrentState\[2\] with stuck data_in port to stuck value GND" {  } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 3 1 0 } }  }  }
{  Warning "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "IDWT97_TOP:IDWT\|IDWT97_Control:Control\|CurrentState\[3\] data_in GND " "Reduced register IDWT97_TOP:IDWT\|IDWT97_Control:Control\|CurrentState\[3\] with stuck data_in port to stuck value GND" {  } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 3 1 0 } }  }  }
{  Warning "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "FDWT97_TOP:FDWT\|FDWT97_Control:Control\|CurrentState\[2\] data_in GND " "Reduced register FDWT97_TOP:FDWT\|FDWT97_Control:Control\|CurrentState\[2\] with stuck data_in port to stuck value GND" {  } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 2 1 0 } }  }  }
{  Warning "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "FDWT97_TOP:FDWT\|FDWT97_Control:Control\|CurrentState\[3\] data_in GND " "Reduced register FDWT97_TOP:FDWT\|FDWT97_Control:Control\|CurrentState\[3\] with stuck data_in port to stuck value GND" {  } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 2 1 0 } }  }  }
{  Warning "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "PcToFPGA:PCFPGA\|ControlPath:A1\|CurrentState\[3\] data_in GND " "Reduced register PcToFPGA:PCFPGA\|ControlPath:A1\|CurrentState\[3\] with stuck data_in port to stuck value GND" {  } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 1 1 0 } }  }  }
{  Warning "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "PcToFPGA:PCFPGA\|DataPath:B1\|Counter_128bits:C1\|Done data_in GND " "Reduced register PcToFPGA:PCFPGA\|DataPath:B1\|Counter_128bits:C1\|Done with stuck data_in port to stuck value GND" {  } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 1 1 0 } }  }  }
{  Info "IMLS_MLS_IGNORED_SUMMARY" "988 " "Ignored 988 buffer(s)" { { Info "IMLS_MLS_IGNORED_SOFT" "988 " "Ignored 988 SOFT buffer(s)" {  } {  } }  } {  }  }
{  Info "IFTM_CARRY_SINGLE_TO_DOUBLE" "12 " "Converted 12 single input CARRY primitives to CARRY_SUM primitives" {  } {  }  }
{  Info "ISCL_SCL_TM_SUMMARY" "8885 " "Implemented 8885 device resources" { { Info "ISCL_SCL_TM_IPINS" "10 " "Implemented 10 input pins" {  } {  } } { Info "ISCL_SCL_TM_OPINS" "9 " "Implemented 9 output pins" {  } {  } } { Info "ISCL_SCL_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" {  } {  } } { Info "ISCL_SCL_TM_LCELLS" "8778 " "Implemented 8778 logic cells" {  } {  } } { Info "ISCL_SCL_TM_RAMS" "80 " "Implemented 80 RAM segments" {  } {  } }  } {  }  }
{  Info "IMPP_MPP_USER_DEVICE" "EP20K400EBC652-1X FDWT_ALL " "Selected device EP20K400EBC652-1X for design FDWT_ALL" {  } {  }  }
{  Info "IFIT_FIT_ATTEMPT" "1 Fri Apr 30 2004 14:23:20 " "Started  fitting attempt 1 on Fri Apr 30 2004 at 14:23:20" {  } {  }  }
{  Info "ITAN_SCC_LOOP" "3 " "Found combinatorial loop of 3 nodes" { { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~56 " "Node sel_level:sel3\|655~56" {  } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } }  } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1410 " "Node sel_level:sel3\|655~1410" {  } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } }  } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1419 " "Node sel_level:sel3\|655~1419" {  } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } }  } }  } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } }  }  }
{  Info "ITAN_SCC_LOOP" "3 " "Found combinatorial loop of 3 nodes" { { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~42 " "Node sel_level:sel3\|655~42" {  } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } }  } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1144 " "Node sel_level:sel3\|655~1144" {  } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } }  } } { Info "ITAN_SCC_NODE" "sel_level:sel3\|655~1153 " "Node sel_level:sel3\|655~1153" {  } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } }  } }  } { { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } } { "FDWT_ALL.v" "" "" { Text "FDWT_ALL.v" 4 1 0 } }  }  }