fdwt_all.csf.msg

這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder

" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"IDWT97_TOP.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"IDWT97_TOP.v\"
" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v\"
" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v\"
" {  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "18 18 F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v " "Found 18 design units and 18 entities in source file F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" { { Info "ISGN_ENTITY_NAME" "1 Counter_128bits " "Found entity 1: Counter_128bits" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" "Counter_128bits" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" 1 -1 0 } }  } } { Info "ISGN_ENTITY_NAME" "2 memory " "Found entity 2: memory" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" "memory" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" 1 -1 0 } }  } } { Info "ISGN_ENTITY_NAME" "3 bidirec " "Found entity 3: bidirec" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" "bidirec" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" 1 -1 0 } }  } } { Info "ISGN_ENTITY_NAME" "4 Counter_State " "Found entity 4: Counter_State" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" "Counter_State" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" 1 -1 0 } }  } } { Info "ISGN_ENTITY_NAME" "5 DataPath " "Found entity 5: DataPath" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" "DataPath" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" 1 -1 0 } }  } } { Info "ISGN_ENTITY_NAME" "6 ControlPath " "Found entity 6: ControlPath" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" "ControlPath" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" 1 -1 0 } }  } } { Info "ISGN_ENTITY_NAME" "7 Chang3to2 " "Found entity 7: Chang3to2" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" "Chang3to2" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" 1 -1 0 } }  } } { Info "ISGN_ENTITY_NAME" "8 PcToFPGA " "Found entity 8: PcToFPGA" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" "PcToFPGA" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" 1 -1 0 } }  } } { Info "ISGN_ENTITY_NAME" "9 FDWT97_Control " "Found entity 9: FDWT97_Control" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" "FDWT97_Control" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" 2 -1 0 } }  } } { Info "ISGN_ENTITY_NAME" "10 FDWT97_Address_R " "Found entity 10: FDWT97_Address_R" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" "FDWT97_Address_R" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" 2 -1 0 } }  } } { Info "ISGN_ENTITY_NAME" "11 FDWT97_DataPath " "Found entity 11: FDWT97_DataPath" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" "FDWT97_DataPath" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" 2 -1 0 } }  } } { Info "ISGN_ENTITY_NAME" "12 FDWT97_TOP " "Found entity 12: FDWT97_TOP" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" "FDWT97_TOP" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" 2 -1 0 } }  } } { Info "ISGN_ENTITY_NAME" "13 IDWT97_Control " "Found entity 13: IDWT97_Control" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" "IDWT97_Control" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" 3 -1 0 } }  } } { Info "ISGN_ENTITY_NAME" "14 IDWT97_Address_R " "Found entity 14: IDWT97_Address_R" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" "IDWT97_Address_R" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" 3 -1 0 } }  } } { Info "ISGN_ENTITY_NAME" "15 IDWT97_DataPath " "Found entity 15: IDWT97_DataPath" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" "IDWT97_DataPath" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" 3 -1 0 } }  } } { Info "ISGN_ENTITY_NAME" "16 IDWT97_TOP " "Found entity 16: IDWT97_TOP" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" "IDWT97_TOP" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" 3 -1 0 } }  } } { Info "ISGN_ENTITY_NAME" "17 sel_level " "Found entity 17: sel_level" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" "sel_level" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" 4 -1 0 } }  } } { Info "ISGN_ENTITY_NAME" "18 FDWT_ALL " "Found entity 18: FDWT_ALL" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" "FDWT_ALL" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" 6 -1 0 } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 C:\\quartus\\libraries\\megafunctions\\lpm_ram_dq.tdf " "Found 1 design units and 1 entities in source file C:\\quartus\\libraries\\megafunctions\\lpm_ram_dq.tdf" { { Info "ISGN_ENTITY_NAME" "1 lpm_ram_dq " "Found entity 1: lpm_ram_dq" {  } { { "C:\\quartus\\libraries\\megafunctions\\lpm_ram_dq.tdf" "lpm_ram_dq" "" { Text "C:\\quartus\\libraries\\megafunctions\\lpm_ram_dq.tdf" 55 1 0 } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 C:\\quartus\\libraries\\megafunctions\\altram.tdf " "Found 1 design units and 1 entities in source file C:\\quartus\\libraries\\megafunctions\\altram.tdf" { { Info "ISGN_ENTITY_NAME" "1 altram " "Found entity 1: altram" {  } { { "C:\\quartus\\libraries\\megafunctions\\altram.tdf" "altram" "" { Text "C:\\quartus\\libraries\\megafunctions\\altram.tdf" 92 1 0 } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 C:\\quartus\\libraries\\megafunctions\\lpm_mux.tdf " "Found 1 design units and 1 entities in source file C:\\quartus\\libraries\\megafunctions\\lpm_mux.tdf" { { Info "ISGN_ENTITY_NAME" "1 lpm_mux " "Found entity 1: lpm_mux" {  } { { "C:\\quartus\\libraries\\megafunctions\\lpm_mux.tdf" "lpm_mux" "" { Text "C:\\quartus\\libraries\\megafunctions\\lpm_mux.tdf" 70 1 0 } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 C:\\quartus\\libraries\\megafunctions\\altshift.tdf " "Found 1 design units and 1 entities in source file C:\\quartus\\libraries\\megafunctions\\altshift.tdf" { { Info "ISGN_ENTITY_NAME" "1 altshift " "Found entity 1: altshift" {  } { { "C:\\quartus\\libraries\\megafunctions\\altshift.tdf" "altshift" "" { Text "C:\\quartus\\libraries\\megafunctions\\altshift.tdf" 34 1 0 } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 C:\\quartus\\libraries\\megafunctions\\muxlut.tdf " "Found 1 design units and 1 entities in source file C:\\quartus\\libraries\\megafunctions\\muxlut.tdf" { { Info "ISGN_ENTITY_NAME" "1 muxlut " "Found entity 1: muxlut" {  } { { "C:\\quartus\\libraries\\megafunctions\\muxlut.tdf" "muxlut" "" { Text "C:\\quartus\\libraries\\megafunctions\\muxlut.tdf" 76 1 0 } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 C:\\quartus\\libraries\\megafunctions\\lpm_decode.tdf " "Found 1 design units and 1 entities in source file C:\\quartus\\libraries\\megafunctions\\lpm_decode.tdf" { { Info "ISGN_ENTITY_NAME" "1 lpm_decode " "Found entity 1: lpm_decode" {  } { { "C:\\quartus\\libraries\\megafunctions\\lpm_decode.tdf" "lpm_decode" "" { Text "C:\\quartus\\libraries\\megafunctions\\lpm_decode.tdf" 64 1 0 } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 C:\\quartus\\libraries\\megafunctions\\lpm_counter.tdf " "Found 1 design units and 1 entities in source file C:\\quartus\\libraries\\megafunctions\\lpm_counter.tdf" { { Info "ISGN_ENTITY_NAME" "1 lpm_counter " "Found entity 1: lpm_counter" {  } { { "C:\\quartus\\libraries\\megafunctions\\lpm_counter.tdf" "lpm_counter" "" { Text "C:\\quartus\\libraries\\megafunctions\\lpm_counter.tdf" 212 1 0 } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf " "Found 1 design units and 1 entities in source file C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" { { Info "ISGN_ENTITY_NAME" "1 alt_synch_counter " "Found entity 1: alt_synch_counter" {  } { { "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" "alt_synch_counter" "" { Text "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" 457 1 0 } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 C:\\quartus\\libraries\\megafunctions\\lpm_add_sub.tdf " "Found 1 design units and 1 entities in source file C:\\quartus\\libraries\\megafunctions\\lpm_add_sub.tdf" { { Info "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Found entity 1: lpm_add_sub" {  } { { "C:\\quartus\\libraries\\megafunctions\\lpm_add_sub.tdf" "lpm_add_sub" "" { Text "C:\\quartus\\libraries\\megafunctions\\lpm_add_sub.tdf" 97 1 0 } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 C:\\quartus\\libraries\\megafunctions\\addcore.tdf " "Found 1 design units and 1 entities in source file C:\\quartus\\libraries\\megafunctions\\addcore.tdf" { { Info "ISGN_ENTITY_NAME" "1 addcore " "Found entity 1: addcore" {  } { { "C:\\quartus\\libraries\\megafunctions\\addcore.tdf" "addcore" "" { Text "C:\\quartus\\libraries\\megafunctions\\addcore.tdf" 73 1 0 } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 C:\\quartus\\libraries\\megafunctions\\a_csnbuffer.tdf " "Found 1 design units and 1 entities in source file C:\\quartus\\libraries\\megafunctions\\a_csnbuffer.tdf" { { Info "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Found entity 1: a_csnbuffer" {  } { { "C:\\quartus\\libraries\\megafunctions\\a_csnbuffer.tdf" "a_csnbuffer" "" { Text "C:\\quartus\\libraries\\megafunctions\\a_csnbuffer.tdf" 10 1 0 } }  } }  } {  }  }