_primary.vhd

在ISE下用verilog开发的16位进位现行加法器

library verilog;
use verilog.vl_types.all;
entity add16_adv is
    port(
        vA              : in     vl_logic_vector(15 downto 0);
        vB              : in     vl_logic_vector(15 downto 0);
        vS              : out    vl_logic_vector(15 downto 0);
        cin             : in     vl_logic;
        cout            : out    vl_logic
    );
end add16_adv;