add16_adv.v

来自「在ISE下用verilog开发的16位进位现行加法器」· Verilog 代码 · 共 64 行

`timescale 1ns/10ps

module add16_adv
(
 vA,
 vB,
 vS,
 cin,
 cout
);
input   [15:0]   vA;
input   [15:0]   vB;  
output   [15:0]  vS;
input            cin;
output           cout;

reg   [15:0]     vS;
reg   [15:0]     vg;
reg   [15:0]     vp;   
reg   [3:0]      vg_;
reg   [3:0]      vp_;
wire  [4:0]      vc_; 
reg   [15:0]     vc;

integer t;
always @(*)
   for(t=0;t<16;t=t+1)begin
        vg[t]=vA[t]&vB[t];
        vp[t]=vA[t]|vB[t];
   end
   
integer   i;
always @(*)
   for(i=0;i<4;i=i+1)begin
        vp_[i]=vp[4*i]&vp[4*i+1]&vp[4*i+2]&vp[4*i+3];
        vg_[i]=vg[4*i+3] | vp[4*i+3]&vg[4*i+2] | vp[4*i+3]&vp[4*i+2]&vg[4*i+1] | vp[4*i+3]&vp[4*i+2]&vp[4*i+1]&vg[4*i+1];
   end 
//------------vc_[4:0]      
assign vc_[0]=cin;   
assign vc_[1]=vg_[0] | vp_[0]&cin;
assign vc_[2]=vg_[1] | vp_[1]&vg_[0] |vp_[1]&vp_[0]&cin;
assign vc_[3]=vg_[2] | vp_[2]&vg_[1] |vp_[2]&vp_[1]&vg_[0] | vp_[2]&vp_[1]&vp_[0]&cin;
assign vc_[4]=vg_[3] | vp_[3]&vg_[2] |vp_[3]&vp_[2]&vg_[1] | vp_[3]&vp_[2]&vp_[1]&vp_[0]&cin;

assign cout = vc_[4];
//------------vc[15:0];
integer j;
always @(*)begin
   for(j=0;j<4;j=j+1)begin
       //j=0;
       vc[4*j+0]=vc_[j];
       vc[4*j+1]=vg[4*j] | vp[4*j]&vc_[j];
       vc[4*j+2]=vg[4*j+1] | vp[4*j+1]&vg[4*j] |vp[4*j+1]&vp[4*j+0]&vc_[j];
       vc[4*j+3]=vg[4*j+2] | vp[4*j+2]&vg[4*j+1] |vp[4*j+2]&vp[4*j+1]&vg[4*j+0] | vp[4*j+2]&vp[4*j+1]&vp[4*j+0]&vc_[j];
   end
end
//-------------vS[15:0]
integer k;
always @(*)
   for(k=0;k<16;k=k+1)begin
       vS[k]=vA[k]^vB[k]^vc[k];
   end
endmodule