string.v

来自「该代码中有不少关于学习verilog HDL的例子,对初学者有帮助」· Verilog 代码 · 共 10 行

module string_test;
reg[8*14:1] stringvar;
initial
  begin
    stringvar="Hello world";
    $display("%s is stored as %h",stringvar,stringvar);
    stringvar={stringvar,"!!!"};
    $display("%s is stored as %h",stringvar,stringvar);
  end
endmodule